YCL DC 101 Search Results

MIL-PRF-6106 LATCH

Abstract: MIL-PRF-6106 3-PDT Latch SO-1065-003
Contextual Info: SERIES YCL ENGINEERING DATA SHEET RELAY - LATCHING 3 PDT, LOW LEVEL TO 10 AMP Magnetic latch operation All welded construction Contact arrangement 3 PDT Qualified to MIL-PRF-6106 PRINCIPLE TECHNICAL CHARACTERISTICS Contacts rated at Low level, 28 Vdc and 115/200

G992

Abstract: MF604F RDPS-POTS050
Contextual Info: Product Specification MF604F File No RDPS-POTS050 Revision R0 System Application Asymmetric Digital Subscriber Line Product Type Micro filter for South Africa Product Name MF604F Date Aug. 27th, 2002 Issued By Sundi Lin - Design Engineer, R&D_1 sundi@ycl.com.tw

WMA-1005

Abstract: WMA-1201
Contextual Info: 10-15Watts Single Output Wallmount adapter WMA series Feature: l l l l l l 90 to 264Vac universal input range. Meet UL/CUL ,TUV ,T-Mark. EMI/RFI meet VDE & FCC limit B. Low cost & compact size. International AC Plug available. 2 Year Warranty. Specifications: typical at nominal line, full load at 25°C.

da53

Abstract: DB26 0195c Outline T39
Contextual Info: 1066 MHz RDRAMâ 256/288 Mb 512Kx16/18x32s Advance Information Overview • The Rambusâ DRAM (RDRAMâ) device is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other

Contextual Info: m o î a ï c MD2258TC-8/10/12 Sem iconductor . DRAFT ADVANCE PRODUCT INFORMATION 262,144 X 2 CMOS High Speed Dynamic RAM Features Pin Definition A8 OlNO WE RAS AO A2 1 2 3 4 5 6 A1 7 C 8 C 9 C < o o Row Access Times of 80/100/120 nS 2:1 Improvement In Density over D ll

Contextual Info: SERIES KA ENGINEERING DATA SHEET RELAY - NONLATCH - AC COIL 4 PDT, 10 AMP 115 Vac and 28 Vac, 400 Hz and 50/400 Hz coil voltages All welded construction Contact arrangement 4 PDT Qualified to MIL-PRF-83536 PRINCIPLE TECHNICAL CHARACTERISTICS Contacts rated at

SO-1055-8690

Abstract: MIL-PRF-83536 Relays
Contextual Info: SERIES JL ENGINEERING DATA SHEET RELAY - LATCH 2 PDT, 12 AMP Magnetic latch operation All welded construction Contact arrangement 2 PDT Designed to the performance standards of MIL-PRF-83536 PRINCIPLE TECHNICAL CHARACTERISTICS Contacts rated at 28 Vdc; 115 Vac, 400 Hz, 1Ø

so-1064

Abstract: SO-1064-00 ycl dc 101
Contextual Info: SERIES X ENGINEERING DATA SHEET RELAY - NONLATCH 2 PDT, LOW LEVEL TO 5 AMP Contact arrangement 2 PDT Qualified to MIL-PRF-6106 PRINCIPLE TECHNICAL CHARACTERISTICS Contacts rated at Low level, 28 Vdc and 115/200 Vac, 400Hz 3Ø, case grounded Weight 0.034lb max

Contextual Info: SERIES KL ENGINEERING DATA SHEET RELAY - LATCH 4 PDT, 12 AMP Magnetic latch operation All welded construction Contact arrangement 4 PDT Qualified at 10Amps to MIL-PRF-83536 PRINCIPLE TECHNICAL CHARACTERISTICS Contacts rated at 28 Vdc; 115 Vac, 400 Hz, and

Contextual Info: IBM04184BSRLAA Prelim in a ry 2 5 6 K X 18 S W S R A M F ea tu r es • 256K x 18 Organizations • Registered Outputs • CMOS Technolgy • Asynchronous Output Enable and Power Down Inputs • Synchronous Pipeline Mode Of Operation with Standard Write • Boundary Scan using limited set ot JTAG 1149.1

12v relay 8 pin diagram

Contextual Info: H April 1999 C - 5 5 File Num ber 2 B 1 4127.2 SLIC Subscriber Line Interface Circuit Features The Harris SLIC incorporates many of the BORSHT function on a single 1C chip. This includes DC battery feed, a ring relay driver, supervisory and hybrid functions. This device is

Contextual Info: 65 ,536 W O R D x 1 6 BIT D Y N A M I C R A M * T h i s is a d v a n c e d i n f o r m a t i o n a n d s p ec if ica ­ t i o n s a r e s u b j e c t to c h a n g e w i t h o u t no tic e. D ESCRIPTION The TC511664JL/ZL is the new generation dynamic RAM organized 65,536 words by 16 bits. The

CAPACITOR 220 HUD

Abstract: ANI 1015
Contextual Info: QUAL I F I CATI ON REQU I REMENT REMOVED M I L - M- 3 8 5 1 0 / 2 3 7 B 25 May 1984 W L R S E D I N G -MI L - M- 3 8 5 1 0 / 2 3 7 A 24 May 1982 MI L I T A R Y SPECI FI CATI ON MI CR OCI R CUI T S , D I G I T A L , MOS, 4096 B I T S T A T I C RANDOM ACCESS MEMORY RAM

1ss nec

Contextual Info: PRELIM INARY DATA S H E E T MOS IN TEGRATED CIRCUIT MC-428LFF72 3.3 V OPERATION 8 M-WORD BY 72-BIT DYNAMIC RAM MODULE BUFFERED TYPE, HYPER PAGE MODE EDO Description Th e M C-428LFF72 1« • 6.388,608 words by 72 bits dynam ic RAM m oduli on which 8 pieces of 84 M DRAM :

RJ754-C-NL

Abstract: 16Kx32 pulse h1012 HB614-1 KS8993 RJ754 reverse MII timing YCL Transformer PH406080 KSZ8993
Contextual Info: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.06 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through

Contextual Info: DM9161A 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver DAVICOM Semiconductor, Inc. DM9161A 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver DATA SHEET Final Version: DM9161A-DS-F01 October 16, 2009 1 Final Version: DM9161A-DS-F01

zilog z84c

Abstract: D-10
Contextual Info: REVISIONS DATE YR-MO-DA DESCRIPTION LTR APPROVED REV SH EET REV SHEET R EV STATUS OF SH EETS RE:V SHEET 1 2 3 PM IC N /A PREPARED BY STANDARDIZED MILITARY DRAWING C H K K E D Í^ THIS DRAWING IS AVAILABLE ' FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE

Contextual Info: 64K X 16 32K x 16 CMOS DUAL-PORT STATIC RAM MODULE 1dt In te g rate d Dev tee Technology, in c . PRELIMINARY IDT7MB1006 IDT7MB1008 FEATURES DESCRIPTION: • High de nsity 1M /512K C M O S du al-po rt static RAM m odule • Fast access tim es: 25 ns m ax.)

DM9000AEP

Abstract: ph163539 YCL ph163539 103-1 MAG-IC DM9000A DM9000AE DM9000A/LQFP48 6170 TC davicom ethernet H1078
Contextual Info: DM9000A Ethernet Controller with General Processor Interface DAVICOM Semiconductor, Inc. DM9000A Ethernet Controller with General Processor Interface DATA SHEET Preliminary Version: DM9000A-DS-P03 Apr. 21, 2005 Preliminary Version: DM9000A-DS-P03 Apr. 21, 2005

YCL ph163112

Abstract: ph163112 AC regulator BT 812 lf-h41s KSZ8721CL S558-5999-U7 TXC10 100BASE-FX KS8721CL FX mode ethernet schematic
Contextual Info: KS8721CL Micrel KS8721CL 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver Rev. 1.0 General Description Features The KS8721CL is a 10BASE-T, 100BASE-TX, and 100BASEFX physical layer transceiver providing MII/RMII interfaces to MACs and switches. Using a unique mixed-signal design that

sq-h48w

Abstract: SQ-H48W Datasheet KS8995XA LF8731 Transpower HB826-2 ycl dc 101 YCL PH406466 YCL PT163020 pin configuration of sq-h48w lan transformer KS8995E
Contextual Info: KS8995XA Integrated 5-Port 10/100 QoS Switch Rev 2.6 General Description The KS8995XA is a highly integrated Layer-2 quality of service QoS switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an

Contextual Info: KS8995XA Integrated 5-Port 10/100 QoS Switch Rev 2.6 General Description The KS8995XA is a highly integrated Layer-2 quality of service QoS switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an

MT4067-10

Abstract: MT4067-12 MT4067-15 M9096 MT4067-20
Contextual Info: iD ISTR B yTIO N _STA TEM EN T^ Approved for public release; distribution is unlim ited. DESC FORM 193 MAY 86 1. SCOPE 1.1 Scope. T h is drawing d e s c rib e s d evice requirem ents f o r c la s s B m i c r o c i r c u i t s i n accordance w ith 1 .2 .1 o f MIL-STD-883, " P r o v is io n s f o r the use o f MIL-STD-883 i n c o n ju n c tio n w i t h c o m p lia n t

LF-H41S

Abstract: Delta LF8505 BT 136 PIN DIAGRAM Manchester CODING DECODING FPGA YCL PT163020 H1102 pt163020 S558-5999-U7 KSZ8721 KS8721B
Contextual Info: KS8721B/BT 2.5V 10/100BasTX/FX MII Physical Layer Transceiver Rev. 2.3 General Description Features Operating at 2.5 volts to meet low voltage and low power requirements, the KS8721B/BT is a 10BaseT/100BaseTX/FX Physical Layer Transceiver, which provides an MII to transmit