XOR FOUR INPUTS Search Results

7486 XOR GATE pin configuration

Contextual Info: The Leader in High Temperature Semiconductor Solutions CHT-7486 DATASHEET Revision: 03.3 Oct. 01, 2012 Last Modified Date High-Temperature, Quad 2-Inputs XOR Gate General Description Features The CHT-7486 contains four independent 2-inputs XOR gates, performing the Boolean function :

Contextual Info: FINAL COM’L: -12.Q-20 Advanced Micro Devices MACH435-12, Q-20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins in PLCC ■ Up to 20 product terms per function, with XOR ■ 128 Macrocells ■ Flexible clocking ■ 12nstpD — Four global clock pins with selectable edges

Contextual Info: 1000EA Family Architectural Description four outputs, which can be configured to be either combinatorial or registered. Inputs to the GLB come from the Global Routing Pool GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that

Contextual Info: P r o d u c t S p e c if ic a t io n < $ 2 iL G 5 Z8615 NMOS Z8 8-BlT MCI Keybo ard Co n tro ller FEATURES • Low Power Consumption - 750 mW ■ 32 Input/Output Lines ■ Digital Inputs NMOS Levels with Internal Pull-Up Resistors ■ 4 Kbytes ROM ■ Four Direct Connect LED Drive Ports

crc-16 implementation

Abstract: toggle type flip flop ic
Contextual Info: TEKTRONIX INC/ TRI ÛUINT EbE D Ì[Q G igaB St B ÔTQbSlô QQ00405 4 EiTRÖ 10G024 10G024K L o g ic Quad D Flip Flop with XOR Inputs 1.9 GHz Clock Rate 10G PicoLogic Family_ FEATURES • Temperature and voltage compensated design • < 50 ps clock to output delay skew

Contextual Info: Lattice p L S r 1016 programmable Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features • PROGRAMMABLE HIGH-DENSITY LOGIC — Member of Lattice’s pLSI Family — High-Speed Global Interconnects — 32 I/O Pins, Four Dedicated Inputs

1032E

Abstract: 1032EA SE140 se 140
Contextual Info: ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

1032E

Abstract: 1032EA
Contextual Info: ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

1032E

Abstract: 1032EA
Contextual Info: ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: 19-2786; Rev 1; 12/03 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ 200Msps Output Update Rate ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -88dBc at fOUT = 10MHz

MAX5883

Abstract: MAX5884 MAX5884EGM MAX5885 MAX5886 MAX5887 MAX5888 Best GSM state transition diagram 30.72MHZ
Contextual Info: 19-2825; Rev 0; 4/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -86dBc at fOUT = 10MHz ACLR = 72dB at fOUT = 30.72MHz

MAX5883

Abstract: MAX5884 MAX5884EGM MAX5885 MAX5886 MAX5887 MAX5888
Contextual Info: 19-2825; Rev 1; 12/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -86dBc at fOUT = 10MHz ACLR = 72dB at fOUT = 30.72MHz

Contextual Info: 19-2825; Rev 1; 12/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ 200Msps Output Update Rate ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -86dBc at fOUT = 10MHz

Contextual Info: 19-2825; Rev 1; 12/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -86dBc at fOUT = 10MHz ACLR = 72dB at fOUT = 30.72MHz

MAX5883

Abstract: MAX5884 MAX5885 MAX5885EGM MAX5886 BTS gsm850
Contextual Info: 19-2786; Rev 0; 4/03 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -88dBc at fOUT = 10MHz ACLR = 74dB at fOUT = 30.72MHz

MAX5885

Abstract: BTS Base Terminal Station MAX5883 MAX5884 MAX5885EGM MAX5886
Contextual Info: 19-2786; Rev 1; 12/03 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -88dBc at fOUT = 10MHz ACLR = 74dB at fOUT = 30.72MHz

Contextual Info: Lattice ispLSr 1016 H I Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs

Contextual Info: Lattice pLSI 1016/883 programmable Large Scale Integration High-Density Programmable Logic Features Functional Block Diagram • PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — MIL-STD-883 Version of the pLS11016 High-Speed Global Interconnects 32 I/O Pins, Four Dedicated Inputs

ISP1016

Abstract: 1016-60 lattice 1016-60LJ Lattice 1016-80LJ 1016E 1016-60LH
Contextual Info: ispLSI 1016 In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — Wide Input Gating for Fast Counters, State

1032E

Abstract: 1032EA
Contextual Info: ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

QFN-48 LAND PATTERN

Contextual Info: 19-2825; Rev 1; 12/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -86dBc at fOUT = 10MHz ACLR = 72dB at fOUT = 30.72MHz

QFN-48 footprint

Abstract: QFN-48 LAND PATTERN
Contextual Info: 19-2786; Rev 1; 12/03 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -88dBc at fOUT = 10MHz ACLR = 74dB at fOUT = 30.72MHz

PLSI 1016-60LJ

Abstract: lattice 1016-60LJ 1016-60LJI LSI1016 1016-60LT44 PLS11016
Contextual Info: Lattice is p L S I Semiconductor Corporation a n d p L S I 1 1 6 High-Density Programmable Logic Features • d lB R I B B E I I d l i H i l B ü l • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs