XO 202 NA Search Results

STACK ORGANISATION

Abstract: l67201 67202
Contextual Info: L 67201/L 67202 MATRA MHS 512 x 9 & 1K × 9 / 3.3 Volts CMOS Parallel FIFO Introduction The L67201/202 implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

Contextual Info: L8C2Q1/2Q2/2Q3/2Q4 L8C201/202/203/204 im 512/1K/2K/4K x 9-bit Asynchronous FIFO DEVICES INCORPORATED FEATURES_ _ □ First-In/First-Out FIFO using Dual-Port Memory □ Advanced CMOS Technology □ High Speed — to 10 ns Access Time □ Asynchronous and Simultaneous

Contextual Info: L8C201/202/203/204 l o g ic 512/1K/2K/4K x 9-bit Asynchronous FIFO DEVICES INCORPORATED FEATURES_ DESCRIPTION □ First-In/First-Out FIFO using Dual-Port Memory □ Advanced CMOS Technology □ High Speed — to 10 ns Access Time □ Asynchronous and Simultaneous

Contextual Info: Tem ic L 67201/L 67202 MATRA MHS 512 x 9 & 1K x 9 / 3.3 Volts CMOS Parallel FIFO Introduction The L67201/202 implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow.

Contextual Info: PRELIMINARY muMHS DATA SHEET_ _ L March 1994 6 7 2 0 1 /L 6 7 2 0 2 512x9 & 1Kx 9 / 3 . 3 VOLTS CMOS PARALLEL FIFO FEATURES . . . . . . . FIRST-IN FIRST-OUT DUAL PORT MEMORY SINGLE SUPPLY 3.3 ±0.3 VOLTS 512 x 9 ORGANISATION L 67201 1024 x 9 ORGANISATION (L 67202)

Contextual Info: L O G IC L 8 C 2 0 1 /2 0 2 /2 0 3 /2 0 4 512/1K/2K/4K x 9-bit Asynchronous FIFO mw DEVICES INCORPORATED DESCRIPTION FEATURES □ First-In/First-Out FIFO using Dual-Port Memory □ Advanced CMOS Technology □ High Speed — to 10 ns Access Time □ Asynchronous and Simultaneous

Contextual Info: TO SHIBA TMP47P202V CMOS 4-Bit Microcontroller TMP47P202VP TMP47P202VM The 47P202V is the system evaluation LSI of 47C102/202 with 16K bits one-time PROM. The 47P202V programs/verifies using an adapter socket to connect with PROM programmer, as it is in TMM27256AD.

47C202

Abstract: 47C102
Contextual Info: TO SHIBA TMP47P202V CMOS 4-BIT MICROCONTROLLER TMP47P202VP TMP47P202VM The 47P202V is the system evaluation LSI of 47C102/202 with 16K bits one-time PROM. The 47P202V programs/verifies using an adapter socket to connect with PROM programmer, as it is in TMM27256AD.

Contextual Info: 2bE D LO GI C D E V I CE S INC • 256/512/1K/2K/4K x 9-bit First-In/First-Out FIFO 55bSTOS Q G G l l S b fl ■ _ T - 9 d~3 S ~ L8C200/201 L8C202/203/204 DESCRIPTION FEATURES □ First-In/First Out (FIFO) using Dual-Port Memory Q Highspeed — tol5 ns Access Time

47c202

Abstract: BM1187 27256 R4945 tmm27256ad 47C102 DIP20-P-300-2 TMP47P202VM TMP47P202VP
Contextual Info: TO SHIBA TMP47P202V CMOS 4-BIT MICROCONTROLLER TMP47P202VP TMP47P202VM The 47P202V is the system evaluation LSI of 47C102/202 with 16K bits one-time PROM. The 47P202V programs/verifies using an adapter socket to connect with PROM programmer, as it is in TMM27256AD.

Contextual Info: Environmental Connectors 233-105-00 MIL-DTL-38999 Series III Type Wall Mount Environmental Receptacle Connector Shell Size 09 = A 11 = B 13 = C 15 = D 17 = E 19 = F 21 = G 23 = H 25 = J Basic Part Number 233-105 - D38999 Series III Type Power Connector Finish Material

Contextual Info: Environmental Connectors 233-105-00 MIL-DTL-38999 Series III Type Wall Mount Environmental Receptacle Connector Shell Size 09 = A 11 = B 13 = C 15 = D 17 = E 19 = F 21 = G 23 = H 25 = J Basic Part Number 233-105 - D38999 Series III Type Power Connector Finish Material

84L14

Abstract: TR54016 TR62411 XRT84L14IQ XRT84V24 T1-403-1995 GPI06
Contextual Info: áç XRT84L14 PRODUCT BRIEF QUAD T1 FRAMER OCTOBER 2000 REV. A1.0.0 GENERAL DESCRIPTION Monitor, Bit Error Rate BER meter, and forced error insertion. The XRT84L14 quad T1/DS1 Framer is a single chip device which integrates 4 T1 framers and transmitters

Contextual Info: CMOS PARALLEL _ FLAGGED FIFO WITH OE 1K x 9, 2K x 9, 4K x 9 IDT72021 IDT72031 IDT72041 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • ID T 7 202 1/03 1/04 1s are high-speed, low -pow er, du al-port m em ory de vice s com m only know n a s FIFO s F irst-In/FirstO ut . D ata can be w ritte n into and read from the m em ory at

Tcon 8.9 f

Abstract: sharp lcd t-con diagram Sharp TCON RTD2020 lcd ttl tcon TCON 30 pin interface LCD Tcon 18BIT ddc2b rtd20 tcon8
Contextual Info: RTD2020 REALTEK FLAT PANEL DISPLAY CONTROLLER RTD2020 Product Brief This document contains introductory information pertaining to the Realtek RTD2020 Flat Panel Display Controller. Because there is proprietary and confidential information contained in the complete specifications, this brief is offered to those interested

Contextual Info: FAST CMOS 16-BIT REGISTER 3-STATE IDT54/74FCT16374T/AT/CT/ET IDT54/74FCT162374T/AT/CT/ET Integrated Device Technology, In c FEATURES: DESCRIPTION: • Common features: - 0.5 MICRON CMOS Technology - High-speed, low-power CMOS replacement for ABT functions

Contextual Info: MU9C7201, MU9C7202 MU9C7203, MU9C7204 5 1 2 X 9 , 1K X 9, 2 K X 9 , AND 4K X 9 CMOS FIFOs OCT ATI DISTINCTIVE CHARACTERISTICS High-speed First-in, First-out buffers 50 ns Access, 65 ns Cycle times 15.4 MHz 512 x 9 ,1 K X 9, 2K X 9, and 4K X 9 organizations

Contextual Info: S E M I C O N D U C T O R S PRODUCT MU9C0591, MU9C1902, MU9C2903, MU9C4904 0.5K X 9, 1 K X 9 , 2 K X 9 , AND 4K X 9 CMOS FIFOs :OR ATIOI DISTINCTIVE CHARACTERISTICS High-speed First-in, First-out buffers Expandable in depth and width with minimal external logic

Contextual Info: MU9C0591, MU9C1902, MU9C2903, MU9C4904 5 1 2 X 9 , 1 K X 9, 2 K X 9 , AND 4K X 9 CMOS FIFOs D, R ELM N # ö p jic z ,lr E DISTINCTIVE CHARACTERISTICS o High-speed First-in, First-out buffers o 20 ns Access time, 30 ns Cycle time 33 MHz o 512 X 9, 1K X 9, 2K X 9,

Contextual Info: 4 TH IS DRAWING 3 IS U N P U B LIS H E D . RELEASED FOR PUBLICATION A L L RIGHTS COPYRIGHT RESERVED. BY TYCO ELECTRONICS CORPORATION. HOUSING COUPLING NUT CLAMP NUT S T A I N L E S S S T E E L PER A S T M - A 4 8 4 AND AST MA582, T Y P E 303 DIELECTRIC

ADN2812

Abstract: ADN2809 ADN2809XCP ADN2809XCP-RL OC48
Contextual Info: a Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier Preliminary Technical Data FEATURES Meets SONET Requirements for Jitter Transfer / Generation / Tolerance Quantizer Sensitivity: 6 mV typical • Adjustable Slice Level: +/- 100 mV

ADN2809

Abstract: ADN2809XCP ADN2809XCP-RL ADN2812 OC48
Contextual Info: PRELIMINARY TECHNICAL DATA a Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier Preliminary Technical Data FEATURES Meets SONET Requirements for Jitter Transfer / Generation / Tolerance Quantizer Sensitivity: 6 mV typical • Adjustable Slice Level: +/- 100 mV

75T203-IP

Abstract: ATB12 75T202-IP
Contextual Info: SSI 75T202/203 m 5V Low-Power DTMF Receiver M M b n s A TDK Group/Company October 1991 FEATURES DESCRIPTION The S S I 75T202 and 75T203 are complete Dual-Tone Multifrequency D T M F receivers detecting a se ­ lectable group of 12 or 16 standard digits. No front-end

Contextual Info: For Information Equipment MN5521 I/O Peripheral Controller for PC/AT Computers Overview The MN5521 is an I/O peripheral controller. It is designed for use in combination with the MN5520A CPU controller and the MN871107 floppy disk drive controller in notebook,