HY514260
Abstract: HY5118160 HY5116160 HY5117404 HY51V65400 HY511616
Text: ré f. 1M x16-bit , 5V, FP, 1/4K r é f. 1 M x16-bit , 3.3V, FP. 1/4K ré f. 1M x16-bit , 5V, EDO, 1/4K , HY51V18160C / HY51V16160C ' HY5118164C / HY5116164C. HY51V18164C / HY51V16164C 1M x16-bit , 3.3V, EDO, 1/4K re f.' 1M x16-bit , 5V, FP. 1/4K r e f . . 1M x16-bit , 3.3V, FP, 1/4K ref. - · 1 Mx 16-bit, 5V, EDO, 1/4K r e t." " 1M x16-bit , 3.3V, EDO, 1/4K ref. 283 291 299 307 315 64M-bit DRAM H Y
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HY531000A.
HY534256A.
256Kx4-bit,
HY512260.
128KX16-bit,
HY514260
HY5118160
HY5116160
HY5117404
HY51V65400
HY511616
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1128K
Abstract: 64K X 4 SRAM
Text: . 185 HY6316100A. 64K x16-bit . 5V, 15/17/20/25ns. 197 HY63V16100A. 64K x16-bit . 3.3V, 20/25/30 , .257 HY6716100.64K x16-bit . 5V, 6/9/12, Pipeline, Syncronous SRAM. 269 HY67V16100. 64K x16-bit . 3.3V, 7/12/17, Pipeline, Syncoronous SRAM. 281 HY6716110.64K x16-bit . 5V, 15/20/25, Non-Pipeline, Syncronous SRAM
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64K-bits
HY6264A.
HY6264A-1.
256K-bits
120ns.
HY2316000.
16-bit.
HY2316050.
1128K
64K X 4 SRAM
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Not Available
Abstract: No abstract text available
Text: , 2K Ref., EDO - 231 1M x16Bit , 5V, 4KRef., FPM - 240 1M x 16 Bit, 5V, 1KRef, FPM - 251 1M x16Bit , 5V, 4KRef., EDO - 262 1M x16Bit , 5V, 1KRef., EDO -274 1M x16Bit , 3.3V, 4KRef., FPM - 286 1M x16Bit , 3.3V, 1M x16Bit , 3.3V, 1M x16Bit , 3.3V, 1M x16Bit , 3.3V, 1KRef, FPM - 297 4KRef
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GM71C4100C
GM71C4100E
GM71C4400C
GM71C4403C
GM71C4400E
GM71C4403E
GM71C4800C
GM71C4260C
GM71C4263C
512Kx8Bit,
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BEDO RAM
Abstract: hy5118160b HY512264 HY5117404 HY5118164B
Text: . 1025 HY5216256. 256K x 16-bit. 2CAS, EDO, HY5216257. 256K x16-bit.2WE , .667 H Y 5118160. 1M x16-bit . FP, 1K r e f . 2CAS, S R , .699 H Y51V 16160B. 1M x16-bit . 3.3V, FP, 4K ref., 2CAS, S R , . 763 H Y51V 16164B. 1M x16-bit . 3.3V, EDO, 4 K ref., 2CAS, S R .779 HY5118164B. 1M x16-bit.EDO , 1 K r e f , 2CAS, S R
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HY531000A.
HY534256A.
16-bit.
HY5216257.
x16-bit.
DB101-20-MAY95
BEDO RAM
hy5118160b
HY512264
HY5117404
HY5118164B
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MAPCA2000
Abstract: X32B DSA00152780 hitachi PLC equator VLIW architecture ac3 decoder toslink PAL to ITU-R BT.601/656 Decoder TV Tuner phillips 21 IEC958 free home theater circuit diagram for assemble
Text: No file text available
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MAP-CA2000TM
MAP-CA2000
MAP-CA2000
128-bit
MAPCA2000
X32B
DSA00152780
hitachi PLC
equator VLIW architecture
ac3 decoder toslink
PAL to ITU-R BT.601/656 Decoder
TV Tuner phillips 21
IEC958
free home theater circuit diagram for assemble
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2005 - DDR2 x32
Abstract: ELPIDA DDR3 DDR3 DRAM layout ddr3 sdram chip datasheets 128mb 512MB xdr elpida DRAM elpida ELPIDA DDR2
Text: x16/x32bit SDRAM, DDR SDRAM and x16-bit DDR2 SDRAM. Printers Digital Video Cameras Improved , processing can be optimized by using x16-bit or x32-bit I/O SDRAM, or DDR SDRAM. We also provide "Bare Chip , appliances. Comparison with two 256Mb DDR2 ( x16-bit configuration) solution IDD4 IDD7 25% Lower
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x32-bit
256Mb
x16-bit
229mA
258mA
172mA
256Mb
512Mb
E0652E90
DDR2 x32
ELPIDA DDR3
DDR3 DRAM layout
ddr3 sdram chip datasheets 128mb
512MB
xdr elpida
DRAM elpida
ELPIDA DDR2
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1997 - AVR 8515 microcontroller
Abstract: PIC16C54 rom based project PIC16C5X PIC16fXX assembly language Programming AT90ICE1200 CCS addressable pwm avr c language application note PIC12C508 PIC16F84 Free Projects of LED Advanced Transdata development board
Text: x16-bit word architecture and they are only comparing their 20-pin version. A better comparison would be , actuality it is 512 x16-bit words AT90S2313 = 2K bytes In actuality PIC16C54 = 768 bytes or 512 x12-bit , actuality it is 1K x16-bit words You have to program the entire 16 bit word for each program instruction , . PIC17CXXX PIC17CXXX's are available from 4K 32K bytes or 2K 16K x16-bit words All devices are OTP and there are some ROM versions In actuality it is 2K x16-bit words AT90S8515 = 8K bytes In actuality
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AT90S1200
DS00170A
AVR 8515 microcontroller
PIC16C54 rom based project
PIC16C5X
PIC16fXX assembly language Programming
AT90ICE1200
CCS addressable
pwm avr c language
application note PIC12C508
PIC16F84 Free Projects of LED
Advanced Transdata development board
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MN1020019
Abstract: MN1020219 QFH064-P-1414B
Text: ⡠MN1020019 / 0219 / 0419 / 0819 â Type MN1020019 / 0219 / 0419 / 0819 1 ROM (x8-bit/ x16-bit ) External /16K / 32K / 64K (External Memory Expandable) 1 RAM (x8-bit/ x16-bit ) 3K /1K / 2K / 3K (External Memory Expandable) 1 Minimum Instruction Execution Time IV1N102D019 / 0219/ 0419/ 0819 :100ns (at 4.5 to 5.5V, 20MHz) IV1N1020019/0219/0419 : 200ns (at 2.7 to 3.3V, 10MHz) 1 Interrupts â¢RESET «Watchdog ⢠Timer Counter 0 to 3 ⢠External 0 to 3 *NMI * Serial ch 0,1 Transmission ⢠Serial ch 0
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MN1020019
x8-bit/x16-bit)
IV1N102D019
100ns
20MHz)
IV1N1020019/0219/0419
200ns
10MHz)
MN1020219
QFH064-P-1414B
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Not Available
Abstract: No abstract text available
Text: . 19 2. KM28N800-T/B . 4.5V~5,5V/1Mx8bit, 512K x16bit.46 3. KM28U160-T/B . 2.7V~3.6V/2Mx8bit, 1M x16bit.48 III.NAND FLASH
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KM28U800-T/B
512Kx16bit.
KM28N800-T/B
x16bit.
KM28U160-T/B
KM29U128T/IT
V/512Kx8bit
V/512Kx8bit.
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2004 - DDR2 x32
Abstract: ELPIDA DDR2 Datasheet Unbuffered DDR2 SDRAM DIMM DDR2 layout 84 FBGA outline DDR2 SDRAM "DDR2 SDRAM" 84 FBGA DDR2 DDR2 x16
Text: required two x16-bit I/O DRAMs. Now, Elpida offers a 512Mb DDR2 SDRAM with x32-bit I/O configuration as a one-chip solution. The advantages of this x32-bit solution over a two 256-megabit DDR2 (with x16-bit
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200/266/333/400/533MHz
400/533/667/800/1066Mbps
x4/x8/x16/x32
100/133/166/200/250MHz
200/266/333/400/500Mbps
E0474ED0
512Mb
DDR2 x32
ELPIDA DDR2
Datasheet Unbuffered DDR2 SDRAM DIMM
DDR2 layout
84 FBGA outline
DDR2 SDRAM
"DDR2 SDRAM"
84 FBGA
DDR2
DDR2 x16
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2003 - Rambus XDR
Abstract: DDR3-1333 XDR Rambus DDR2 x32 ELPIDA DDR3 XDR DRAM DDR2-667 DDR2-800 DDR333 DDR400
Text: , through 3.2Gbps, 4.0Gbps, 4.8Gbps ultra-high-speed data transfer operation and x16-bit I/O configuration , applications. Features of XDR DRAM Highest pin bandwidth DRAM Bandwidth 10.0 GB/s ( x16-bit base
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512Mb
x16-bit
GDDR3-1600
DDR3-1333
64MB/system
DDR2-667
DDR2-1066
Rambus XDR
DDR3-1333
XDR Rambus
DDR2 x32
ELPIDA DDR3
XDR DRAM
DDR2-667
DDR2-800
DDR333
DDR400
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MN102L35G
Abstract: QMN102L35G PX-ICE102L00
Text: QMN102L35G 1 Type MN102L35G 1 ROM ( x16-Bit ) 144 K 1 RAM ( x16-Bit ) 5 K 1 Minimum Instruction Execution Time 167 ns (at 4.75 V to 5.25 V, 12 MHz) 1 Interrupts External (4 lines) Internal (23 lines) â Timer x 8, A/Dx 1, Undefined command x1, RESET x1, OSDx2, Serial x 2, l2C x 1, Caption x 2, Remote Control x 1, Address coincidence x 4 1 Timer Counter 8-Bit timer x 2 16-Bit timer x 2 Watchdog timer: 17-Bit x 1 1 Serial Interface l2C x 1 For multimaster mode, Bus line
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QMN102L35G
MN102L35G
x16-Bit)
16-Bit
17-Bit
SDIP064-P-0750
PX-ICE102L00
PX-PRB102L35
MM102LP35G
MN102L35G
QMN102L35G
PX-ICE102L00
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OSC 20Mhz
Abstract: MN102L230 QFP160-P-2828B tv remote control system osc20mhz 521K
Text: ⡠MN102L230 1 Type MN102L23Q I ROM (x8-bit / x16-bit ) Maximum 16M in external total (Control register, Inbuilt RAM, Character multiplex l/F space, VRAM, DRAM. Reserve Space included) â RAM ( x16-bit ) 2K I Minimum Instruction Execution Time 100ns (at 4.5 to 5.5V, 20MHz) 1 Interrupts External 4 Internal 6 : Timer x 2, A/D x 1, TV peripheral block x 1, Watchdog x 1, NMI x 1 TV peripheral block internal interrupt : OSD x 4, Serial x 2, l2C x 1, MUSE x 4, Remote Control x 5 1 Timer Counter
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MN102L230
MN102L23Q
x16-bit)
100ns
20MHz)
16-bit
1000-diviston
17-bit
20Qfi,
OSC 20Mhz
MN102L230
QFP160-P-2828B
tv remote control system
osc20mhz
521K
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Not Available
Abstract: No abstract text available
Text: J MN1020019 / 0219 / 0419 / 0819 MN1020019 / 0219 / 0419 / 0819 1 Type 1 ROM (x8-bit/ x16-bit ) External / 1 6K / 32K / 64K (External Memory Expandable) 1 RAM (x8-bit/ x16-bit ) 3K / 1 K / 2K / 3K (External Memory Expandable) I Minimum Instruction Execution Time MN1020019 / 0219 / 0419 / 0819 : 100ns (at 4.5 to 5.5V, 20MHz) MN1020019 / 0219 / 0419 1 Interrupts â¢RESET : 200ns (at 2.7 to 3,3V, 10MHz) »Watchdog «Timer Counter 0 to 3 ⢠External 0 to 3
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MN1020019
x8-bit/x16-bit)
100ns
20MHz)
200ns
10MHz)
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8X16
Abstract: 048576-WORD 16MCDRAM
Text: Preliminary Spec. (Rev.0.6) msm^TStp 16MCDRAM : 16k (lk-WORD X16-BIT ) SRAM Cache, TAG, IWI^IVIt V I U I UWM I r Comparator, built-in Controller 16M(1M-W0RD X 16-BIT)DRAM PRELIMINARY This document is a preliminary specification and some of the contents are subject to change without notice. DESCRIPTION ⢠This 16M-bit Cache DRAM integrates a 1,048576-word by 16-bit dynamic memory array, a 1024 , (REVO,6)Oct.1994 Preliminary Spec. (Rev.0.6) msm^TStp 16MCDRAM : 16k (lk-WORD X16-BIT ) SRAM Cache, TAG
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16MCDRAM
X16-BIT)
16-BIT
16M-bit
048576-word
1024-word
8X16
16MCDRAM
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2005 - TC58NVG2D4BFT00
Abstract: TH58NVG3D4BFT00 SSTL-18 TMP86FS49FG H5401 TH58NVG*D TC58DVG14B1FT00 SSTL18 th58nvg TMP86FS49UG
Text: -50 TC59LM913AMG-55 TC59LM913AMG-60 I/O x8bit SSTL_18, HSTL x16bit x8bit SSTL_2 x16bit
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03-3457-3405FAX.
TC58NVG2D4BFT00/TH58NVG3D4BFT00
TC58DVG14B1FT00
TC58NVG2D4BFT00
TH58NVG3D4BFT00
600s/
TC58NVG2D4BFT00
TH58NVG3D4BFT00
SSTL-18
TMP86FS49FG
H5401
TH58NVG*D
SSTL18
th58nvg
TMP86FS49UG
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X16-BIT
Abstract: 64K SRAM
Text: HY62UF16101C S eries 64K x16bit full CMOS SRAM DESCRIPTION The HY62UF16101C is a high speed, super low power and 1M bit full CMOS SRAM organized as 65,536 words by 16bit. The HY62UF16101C uses high , is written or read to the Upper byte, I/O 9 -I/O 16. 194 HY62UF16101C S eries 64K x16bit full , LOADS V t M=2.8V Note 1. Including jig and scope capacitance HY62UF16101C S eries 64K x16bit , HY62UF16101C S eries 64K x16bit full CMOS SRAM MARKING INSTRUCTION Package Marking Example H Y
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HY62UF16101C
x16bit
16bit.
HYUF611CC
100ns
X16-BIT
64K SRAM
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2003 - playstation 3
Abstract: playstation SONY PLAYSTATION 3 playstation controller XDR Rambus DDR2-667 DDR2-800 DDR333 DDR400 104BA
Text: a single device, through 3.2GHz (4.0GHz) ultra-high-speed data transfer operation and x16-bit I/O , XDR DRAM DRAM Bandwidth x16-bit base DDR333 0.6GB/s DDR400 0.8GB/s DDR2-667 1.3GB
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512Mb
E0428E60
playstation 3
playstation
SONY PLAYSTATION 3
playstation controller
XDR Rambus
DDR2-667
DDR2-800
DDR333
DDR400
104BA
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pin details of VIPER 22
Abstract: SDRAM DIMM 1997 SDRAM 1997 82C576 VIPer 32 opti chipset 82C579
Text: see the following fanout: · Minimum four input loads in a system with DIMMs using x16bit devices · , following fanout: · Minimum one input load in a system with a single DIMM using x16bit devices · Maximum , following fanout: · Minimum four input load in a system with a single DIMM using x16bit devices · Maximum , x16bit devices · Maximum 64 input loads in a system with four single-bank (or two double-bank) DIMMs , single DIMM using x16bit devices · Maximum 64 input loads in a system with four single-bank (or two
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82C579
82C579.
100ns
200ns
pin details of VIPER 22
SDRAM DIMM 1997
SDRAM 1997
82C576
VIPer 32
opti chipset
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qfp128p
Abstract: No abstract text available
Text: IVI N 1 020012A / 0012AFA / 0012-3V 1 Type | R O M (x8-bit/ x16-bit ) R A M (x8-bit/ x16-bit ) External ROM, RAM MN1020012A / 0012AFA : 100ns (at 4.5 to 5.5V, 20MHz) MN1020012-3V : 200ns (at 3.0 to 3.6V, 10MHz) M N 1 020012A / 0 0 1 2 A F A / 0012-3V Maximum 16M In total (Special Register 1K, Reserve Space 3K included) | Minimum Instruction Execution Time | Interrupts · RESET «Watchdog «Tim er Counter 0 to 9 «Tim er Counter 10 to 12 ·T im e r Counter 10 to 12 Compare Capture A «Tim er
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20012A
0012AFA
012-3V
x8-bit/x16-bit)
MN1020012A
0012AFA
100ns
20MHz)
MN1020012-3V
qfp128p
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mk22fn
Abstract: KE06
Text: ) Random Number Generator Timers Analog Up to 2 x16bit ADC Communication Interfaces 3xI2C , Generator Analog Up to 2 x16bit ADC 3 x ACMP Up to 2 x 12-bit DAC Cryptographic Acceleration , Communication Interfaces Up to 2 x16bit ADC Cryptographic Acceleration Unit (CAU) Carrier Modulator , Analog 2 x16-bit ADC Timers Communication Interfaces FlexTimer 2xI2C 1xI2S 2 x ACMP , Program Flash Up to 512K Low-Leakage Wake-Up Unit Security and Integrity Analog â¢2 x16-bit
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2005 - sdram pin voltage
Abstract: DRAM elpida elpida SDRAM
Text: popularization of broadband. To meet market demand, we provide low power and lower density x16-bit 64Mb/128Mb , demands driving the digital video camera market. Video processing can be optimized by using x16-bit or
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210mA
140mA
256Mb
512Mb
E0652E40
sdram pin voltage
DRAM elpida
elpida SDRAM
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L25D
Abstract: L2503 L25A LP25A MN102L2503 MN102LP25G MN102L25A LP25D LP25Z
Text: ⡠MN102LP25G / L25G / LP25Z / LF25Z / L25Z / LP25D / L25D / LP25A / L25A / L2503 â Type MN102LP25G / L25G / LP25Z / LF25Z / L25Z / LP25D / L25D / LP25A / L25A / L2503 (For MN102LP25G and L25G, ES samples are available. LF25Z, LP25A and L25A are under development.) â ROM (x8-bit/ x16-bit ) 128K (OTP) / 128K / 128K (OTP) / 128K (Flash) / 128K / 64K (OTP) / 64K / 32K (OTP) / 32K / External I RAM (x8-bit/ x16-bit ) 5K/5K/3K/3K/3K/3K/3K/2K/2K/3K I Minimum Instruction Execution Time â Interrupts All models
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MN102LP25G
LP25Z
LF25Z
LP25D
LP25A
L2503
L25D
L2503
L25A
MN102L2503
MN102L25A
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pa5ad
Abstract: IR07 AD03 AD04 MN102L360C MN102L36K OK-32K
Text: ⡠MN102L36K / L360C 1 Type MN102L36K [ES (Engineering Sample) available] / L360C 1 ROM (x8-Bit/ x16-Bit ) 256 K/ External 1 RAM (x8-Bit/ x16-Bit ) 10 K/5 K 1 Minimum Instruction Execution Time 100 ns (at 4.5 V to 5.5 V, 20 MHz) 200 ns (at 2.7 V to 3.6 V, 10 MHz) 1 Interrupts ⢠RESET ⢠Watchdog ⢠Timer Counter 0 to 5 ⢠Fixed-Length Serial ch 0,1 Transmission ⢠Fixed-Length Serial Ch 0,1 Reception ⢠Timer Counter 6 to 7 ⢠Timer Counter 6 to 7 Compare Capture A ⢠Timer
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MN102L36K
L360C
MN102L36K
x8-Bit/x16-Bit)
LQFP128-P-1818C
MN102L360C
MN102L36xx
128pin
pa5ad
IR07
AD03
AD04
MN102L360C
OK-32K
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Not Available
Abstract: No abstract text available
Text: MN102L35G |Typ e | MN102L35G (under development) 144K 5K ROM ( x16-bit ) | RAM ( x16-bit ) | Minimum Instruction Execution Time | Interrupts External (4 lines) 1 6 7 n s (at 4 .7 5 to 5 .2 5 V , 12M H z) Internal (23 lines) Timer x 8, A/D x 1, Undefined command x 1, RESET x 1, OSD x 2, Serial x 2, l2C x 1, Caption x 2, Remote Control x 1, Address coincidence x 4 | Timer Counter 8 -b it tim er x 2 1 6 -b it tim er x 2 W atchd og tim er: 1 7 -b it x 1 | Serial Interface | Caption
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MN102L35G
x16-bit)
SDIP064-P-0750
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