VQFN FOOTPRINT 6MM Search Results
VQFN FOOTPRINT 6MM Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| CSD95480RWJT |
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70A Synchronous Buck NexFET™ Smart Power Stage in an Industry Standard Footprint 41-VQFN-CLIP -55 to 150 |
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| CSD95480RWJ |
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70A Synchronous Buck NexFET™ Smart Power Stage in an Industry Standard Footprint 41-VQFN-CLIP -55 to 150 |
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| DP83TC813SRHFTQ1 |
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Automotive Low-Power, Small Footprint 100BASE-T1 Ethernet PHY (SGMII) 28-VQFN -40 to 125 |
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| CSD95482RWJT |
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40A Synchronous Buck NexFET™ Smart Power Stage in an Industry Standard Footprint 41-VQFN-CLIP -55 to 150 |
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| CSD95481RWJ |
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60A Synchronous Buck NexFET™ Smart Power Stage in an Industry Standard Footprint 41-VQFN-CLIP -55 to 150 |
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VQFN FOOTPRINT 6MM Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: CDCLVD1212 www.ti.com SCAS901B – SEPTEMBER 2010 – REVISED JANUARY 2011 2:12 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1212 FEATURES 1 • • • • • • • • • • • • 2:12 Differential Buffer Low Additive Jitter: <300 fs RMS in |
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CDCLVD1212 SCAS901B EIA/TIA-644A 40-Pin | |
40spqContextual Info: CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 Dual 1:6 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2106 FEATURES 1 • • • • • • • • • • • • Dual 1:6 Differential Buffer Low Additive Jitter: <300 fs rms |
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CDCLVD2106 SCAS902B EIA/TIA-644A 40-pin CDCLVD2106 40spq | |
VQFN footprint 6mm
Abstract: CDCLVD1212
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CDCLVD1212 SCAS901B EIA/TIA-644A 40-Pin CDCLVD1212 VQFN footprint 6mm | |
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Contextual Info: CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 Dual 1:6 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2106 FEATURES 1 • • • • • • • • • • • • Dual 1:6 Differential Buffer Low Additive Jitter: <300 fs rms |
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CDCLVD2106 SCAS902B EIA/TIA-644A 40-pin | |
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Contextual Info: CDCLVD1212 www.ti.com SCAS901B – SEPTEMBER 2010 – REVISED JANUARY 2011 2:12 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1212 FEATURES 1 • • • • • • • • • • • • 2:12 Differential Buffer Low Additive Jitter: <300 fs RMS in |
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CDCLVD1212 SCAS901B EIA/TIA-644A 40-Pin | |
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Contextual Info: CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 Dual 1:6 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2106 FEATURES 1 • • • • • • • • • • • • Dual 1:6 Differential Buffer Low Additive Jitter: <300 fs rms |
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CDCLVD2106 SCAS902B EIA/TIA-644A 40-pin CDCLVD2106 | |
CDCLVP1212Contextual Info: CDCLVP1212 www.ti.com. SCAS886 – AUGUST 2009 12 LVPECL Output, High-Performance Clock Buffer |
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CDCLVP1212 SCAS886 CDCLVP1212 | |
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Contextual Info: CDCLVP1212 www.ti.com. SCAS886 – AUGUST 2009 12 LVPECL Output, High-Performance Clock Buffer |
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CDCLVP1212 SCAS886 10-kHz 20-MHz | |
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Contextual Info: CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 Dual 1:6 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2106 FEATURES 1 • • • • • • • • • • • • Dual 1:6 Differential Buffer Low Additive Jitter: <300 fs rms |
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CDCLVD2106 SCAS902B EIA/TIA-644A 40-pin | |
CDCLVP2106
Abstract: QFN-40 weight
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CDCLVP2106 SCAS887 CDCLVP2106 QFN-40 weight | |
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Contextual Info: CDCLVP2106 SCAS887A – SEPTEMBER 2009 – REVISED AUGUST 2011 www.ti.com 12 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP2106 FEATURES DESCRIPTION • • • The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL |
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CDCLVP2106 SCAS887A CDCLVP2106 | |
VQFN footprint 6mmContextual Info: CDCLVP2106 www.ti.com. SCAS887 – SEPTEMBER 2009 12 LVPECL Output, High-Performance Clock Buffer |
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CDCLVP2106 SCAS887 10-kHz 20-MHz VQFN footprint 6mm | |
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Contextual Info: CDCLVP1212 www.ti.com SCAS886A – AUGUST 2009 – REVISED MAY 2010 12 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1212 FEATURES DESCRIPTION • • • The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL |
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CDCLVP1212 SCAS886A 10-kHz 20-MHz QFN-40 | |
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Contextual Info: CDCLVP2106 SCAS887A – SEPTEMBER 2009 – REVISED AUGUST 2011 www.ti.com 12 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP2106 FEATURES DESCRIPTION • • • The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL |
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CDCLVP2106 SCAS887A 10-kHz 20-MHz QFN-40 | |
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VQFN footprint 6mmContextual Info: CDCLVP1212 www.ti.com SCAS886A – AUGUST 2009 – REVISED MAY 2010 12 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1212 FEATURES DESCRIPTION • • • The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL |
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CDCLVP1212 SCAS886A 10-kHz 20-MHz QFN-40 VQFN footprint 6mm | |
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Contextual Info: CDCLVP1212 SCAS886B – AUGUST 2009 – REVISED AUGUST 2011 www.ti.com 12 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1212 FEATURES DESCRIPTION • • • The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL |
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CDCLVP1212 SCAS886B 10-kHz 20-MHz QFN-40 | |
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Contextual Info: CDCLVP1212 SCAS886B – AUGUST 2009 – REVISED AUGUST 2011 www.ti.com 12 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1212 FEATURES DESCRIPTION • • • The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL |
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CDCLVP1212 SCAS886B CDCLVP1212 | |
CDCLVP2106Contextual Info: CDCLVP2106 www.ti.com. SCAS887 – SEPTEMBER 2009 12 LVPECL Output, High-Performance Clock Buffer |
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CDCLVP2106 SCAS887 CDCLVP2106 | |
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Contextual Info: CDCLVP1212 SCAS886B – AUGUST 2009 – REVISED AUGUST 2011 www.ti.com 12 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1212 FEATURES DESCRIPTION • • • The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL |
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CDCLVP1212 SCAS886B CDCLVP1212 | |
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Contextual Info: TPS65250 www.ti.com SLVSAA3B – JUNE 2010 – REVISED JANUARY 2011 4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE CIRCUIT Check for Samples: TPS65250 FEATURES 1 • • |
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TPS65250 | |
D link schematic circuit diagram adsl modem board
Abstract: TDK-SLF7055
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TPS65250 D link schematic circuit diagram adsl modem board TDK-SLF7055 | |
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Contextual Info: TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE CIRCUIT Check for Samples: TPS65250 FEATURES 1 • • |
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TPS65250 | |
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Contextual Info: TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE CIRCUIT Check for Samples: TPS65250 FEATURES 1 • • |
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TPS65250 | |
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Contextual Info: TPS65250 www.ti.com SLVSAA3B – JUNE 2010 – REVISED JANUARY 2011 4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE CIRCUIT Check for Samples: TPS65250 FEATURES 1 • • |
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TPS65250 | |