VQC 10 Search Results

phl 248 y

Abstract: SN54AHC257
Contextual Info: SN54AHC257, SN74AHC257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS S CLS349 - MAY 1996 Operating Range 2-V to 5.5-V Vqc EP/C Enhanced-Performance Implanted

Contextual Info: DS1833 DALLAS SEMICONDUCTOR DS1833 5V EconoReset PIN ASSIGNMENT FEATURES • Automatically restarts microprocessor after power failure • Maintains active-high reset for 350 ms after turns to an in-tolerance condition Vqc re­ • Accurate 5%, 10% or 15% microprocessor 5V power

2BF010

Contextual Info: TMS28F010B 1048576-BIT FLASH MEMORY SMJS824A-MAY 1995 - REVISED JUNE 1995 Organization . . . 128K x 8-Bit Flash Memory Pin Compatible With Existing 1-Megabit EPROMs Vqc Tolerance ±10% All Inputs/Outputs TTL Compatible Maximum Access/Minimum Cycle Time ’2BF010B-90 90 ns

Contextual Info: DS1321 PRELIMINARY DALLAS SEMICONDUCTOR DS1321 Flexible Nonvolatile C ontroller with Lithium Battery M onitor FEATURES PIN ASSIGNM ENT • Converts CMOS SRAM into nonvolatile memory • Unconditionally write-protects SRAM when Vqc ¡s out of tolerance 3 VCC|

A17J

Contextual Info: 54AC11034,74AC11034 HEX NONINVERTERS D2957, FEBRUARY 1988 - REVISED APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-PIn Vqc and GND Configurations Minimize High-Speed Switching Noise EPICm Enhanced-Performance Implanted CMOS 1-|im Process

Contextual Info: 54AC11032,74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES D2957, JULY 1987 - REVISED APRIL 1993 54AC11032. . . J PACKAGE 74AC11032 . . . D, DB OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-PIn Vqc and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: SN54AHC245, SN74AHC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS23QB- OCTOBER 1995 - REVISED MARCH 1996 Operating Range 2-V to 5.5-V Vqc EPIC"* Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17

Contextual Info: TLV2361, TLV2361Y, TLV2362, TLV2362Y HIGH-PERFORMANCE LOW-VOLTAGE OPERATIONAL AMPLIFIERS _SLOS195A - FEBRUARY 1997 - REVISED MARCH 1998 • Low Supply Voltage Operation . . . Vqc = ± 1 V Min • Wide Bandwidth . . . 7 MHz Typ at VCC± = ±2.5V •

ci-42

Abstract: 74ACT11014
Contextual Info: 74ACT11014 HEX SCHMITT-TRIGGER INVERTER SCAS142A- D3791, FEBRUARY 1991 - REVISED APRIL 1993 DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout 1Y[ 1 2Y[ 2 3Y[ 3 Center-Pin Vqc and GND Configurations

1245Y

Contextual Info: DS 1245Y/A B DALLAS SEMICONDUCTOR FEATURES DS1245Y/AB 1024K Nonvolatile SRAM PIN ASSIGNMENT I 1 A14 • Data is automatically protected during power loss I 1 1 32 1 2 3 31 • Unlimited write cycles • Low-power CMOS • Full ±10% Vqc operating range DS1245Y

74AC108

Abstract: so 54 t 74AC11066
Contextual Info: 54AC11086, 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES TI0152— D3375, N O VEM BER 1989 • Flow-Through Architecture to Optimize PCB Layout 54AC11086 . . . J PACKAGE 74AC11086 . . . D OR N PACKAGE TOP VIEW • Center-Pin Vqc and GND Configurations to

Contextual Info: SN54AHC273, SN74AHC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS376A Operating Range 2-V to 5.5-V Vqc EPIC Enhanced-Performance Implanted CMOS Process JUNE 1997-REVISED DECEMBER 1997 SN54AHC273 . . . j\> R V$ PACKAGE SN74AHC273 . . . DB, DGV, DW, N, OR PW PACKAGE

Contextual Info: CDC587 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS562B- DECEMBER 1996 - REVISED JULY 1998 DQG PACKAGE TOP VIEW • Operates at 3.3-V Vqc • Distributes One Clock Input to 16 Outputs • Four Select Inputs Configure Output

Voltage Supervisors

Abstract: D330
Contextual Info: TL7702BM, TL7705BM SUPPLY VOLTAGE SUPERVISORS D3303. SEPTEMBER 1989-REVISED MARCH 1992 JG PACKAGE Power-On Reset Generator TOP VIEW Automatic Reset Generation After Voltage Drop REF[ U RESIN[ 2 CT[ 3 GND[ 4 Defined Output From Vqc a 1 V Precision Voltage Sensor

Contextual Info: CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _ SCAS446B - JULY 1994- REVISED FEBRUARY 1996 Low Output Skew for Clock-Dlstrlbutlon and Clock-Generatlon Applications Operates at 3.3-V Vqc Distributes Differential LVPECL Clock

Contextual Info: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES D2957. JUNE 1987-R E V IS E D APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin Vqc and GND Configurations Minimize High-Speed Switching Noise EPIC'“ Enhanced-Pertormance Implanted CMOS 1-^m Process

Contextual Info: CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS378D - APRIL 1994 - REVISED APRIL 1996 • Low-Output Skew for Clock-Dlstrlbution and Clock-Generation Applications • • • Operates at 3.3-V Vqc Distributes One Clock Input to Six Outputs

AHC540

Abstract: SN54AHC540 SN74AHC540
Contextual Info: SN54AHC540, SN74AHC540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS260C - DECEMBER 1995 - REVISED JUNE 1996 Operating Range 2-V to 5.5-V Vqc SN54AHC 540 . . . J OR W PACKAGE SN74AHC 540 . . . DB, DW, N, OR PW PACKAGE TO P VIEW EPIC (Enhanced-Performance Implanted

Contextual Info: in te l 28F016XS 16-MBIT 1 MBIT x 16, 2 MBIT x 8 SYNCHRONOUS FLASH MEMORY Effective Zero Wait-State Performance up to 33 MHz — Synchronous Pipelined Reads Backwards-Compatible with 28F008SA Command-Set SmartVoltage Technology — User-Selectable 3.3V or 5V Vqc

LCX02

Abstract: 74LCX02 74LCX02M 74LCX02MTC 74LCX02MTCX 74LCX02MX 74LCX02SJ 74LCX02SJX
Contextual Info: LCX02 & National Semiconductor 74LCX02 Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs Supports live insertion/withdrawal 2.0V-3.6V Vqc supply operation 24 mA output drive Implements patented Quiet Series noise/EMI reduc­ tion circuitry Functionally compatible with 74 series 02

SN74AHC541

Contextual Info: SN74AHC541 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCLS261B - DECEMBER 1996 - REVISED JANUARY 1996 DB, DW, N, OR PW PACKAGE TOP VIEW • Operating Range: 2-V to 5.5-V Vqc • EPIC (Enhanced-Performance Implanted CMOS) Process • Package Options Include Plastic

RADIO RECEIVER IC

Abstract: 0217k 528D 3017b
Contextual Info: Ü5 -i* 7 ACîiïU • «tM aH uW W M u*- . M onolithic Linear IC 3017B . Ol 5W A F Power Amplifier 528D -f :- ‘- ~. :■■■ Features ■ - ■ -~.v t ~ [ \ - • ■>/ . ,. Output- power 10.5W- typ ‘ Vqc=6V, Rj^Sphms, THD=1D%. .low, quiescent'currèntr'',

Contextual Info: SN54AHC541, SN74AHC541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS261F- DECEMBER 1995 - REVISED JUNE 1996 Operating Range 2-V to 5.5-V Vqc EPIC1" Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17

Contextual Info: 54AC11010,74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES D2957, MAY 1987 - REVISED APRIL 1983 Flow-Through Architecture Optimizes PCB Layout Center-PIn Vqc and GND Configurations Minimize High-Speed Switching Noise EP IC “ Enhanced-Performance Implanted CMOS 1-|j.m Process