VCO IF Search Results

Contextual Info: ICS2694 Integrated Circuit Systems, Inc. Motherboard Clock Generator Features Applications • Low cost - eliminates multiple oscillators and Count Down Logic • CPU clock and Co-processor clock • Hard Disk and Floppy Disk clock Primary VCO has 16 Mask Programmable frequencies

Contextual Info: TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136B – APRIL 1996 – REVISED JANUARY 2002 D D D D D D D Voltage-Controlled Oscillator VCO Section: – Ring Oscillator Using Only One External Bias Resistor (RBIAS) – Lock Frequency: 43 MHz to 100 MHz (VDD = 5 V ±5%,

Contextual Info: H M C 1 3 1 C 8 MICROWAVE CORPORATION G a A s M M IC SM T B U F F E R E D C -B A N D VC O F E B R U A R Y 1998 Features General Description 1 GHz TUNING RANGE The HMC131C8 is a SMT C-Band VCO SINGLE +5V SUPPLY OPERATION with on-chip buffering for improved load iso­

Contextual Info: HD155111F RF Single-chip Linear IC for PCN Cellular Systems HITACHI ADE-207-257 Z 1st Edition August 1998 Description The HD 15511 IF was developed for PCN (DCS 1800) cellular systems, and integrates most of the functions of a transceiver. The HD 15511 IF incorporates the bias circuit for a RF LNA, a 1st mixer, lst-IF amplifier,

Contextual Info: TRF4900 SINGLEĆCHIP RF TRANSMITTER SLWS092G − JULY 2000 − REVISED FEBRUARY 2005 D Single-Chip RF Transmitter for 868-MHz D D D D D D D D D Typical Output Frequency Resolution of and 915-MHz ISM Bands 850-MHz to 950-MHz Operation FM/FSK Operation for Transmit

Contextual Info: H D 153021F Preliminary 25-M bp s V F O with Built-in 1-7 E n co d e r/ D e co d e r Description The HD153021F is a 25-Mbps VFO with built-in 1-7 run-length-limit encoder/decoder developed for use in magnetic disk drives. In read mode it decodes 1-7 RLL encoded data from the magnetic

PJ 966 IV

Contextual Info: ADE-207-039 HD153021F 25-Mbps VFO with Buit-in 1-7 Encoder/Decoder ^ H IT A C H I Mar. 1990 x Description The HD153021F is a 25-Mbps VFO with built-in 1-7 run-length-limit encoder/decoder developed for use in magnetic disk drives. In read mode it decodes 1-7 RLL encoded data from the magnetic

Contextual Info: ICS1574 Integrated Circuit Systems, Inc. User Programmable Laser Engine Pixel Clock Generator Description Features The ICS1574 is a very high performance monolithic phaselocked loop PLL frequency synthesizer designed for laser engine applications. Utilizing ICS’s advanced CMOS mixed­

Contextual Info: QS5LV931 ADVANCE INFORMATION 3.3V Low Skew CMOS PLL Clock Driver With Integrated Loop Filter Q u a l it y S e m ic o n d u c t o r , I n c . DESCRIPTION FEATURES/BENEFITS JEDEC LVTTL compatible level Clock input is 5V tolerant Q outputs, Q/2 output < 300ps output skew, Q0-Q4

Contextual Info: Integrated Circuit System s, Inc. ICS9161A Dual Programmable Graphics Frequency Generator General Description Features The ICS9161A is a fully programmable graphics clock generator. It can generate user-specified clock frequencies using an externally generated input reference or a single

Contextual Info: HD155008T Built-in 1.1 GHz / 460 MHz High Speed Prescaler Dual PLL Frequency Synthesizer IC HITACHI ADE-207-239 Z Preliminary, 1st. Edition November 1997 Description The HD155008T is a dual PLL frequency synthesizer IC that was developed for mobile telecommunication

Contextual Info: ICS1561A Integrated Circuit Systems, Inc. Product Preview Differential Output Video Dot Clock Generator Description Features High Frequency operation for extended video m odes up to 230 M Hz Com patible with Brooktree high perform ance R A M ­ DACs Low Cost - Elim inates need for multiple ECL crystal

Contextual Info: AV9173-15 Integrated Circuit Systems, Inc. Video Genlock PLL General Description Features The AV9173-15 provides the analog circuit blocks required for implementing a video genlock dot pixel clock generator. It contains a phase detector, charge pump, loop

Contextual Info: AV9173-01 Integrated Circuit Systems, Inc. Video Genlock PLL General Description Features The AV9173-01 provides the analog circuit blocks required for im plem enting a video genlock dot pixel clock generator. It contains a phase detector, charge pump, loop

Contextual Info: SIEMENS GSM Receiver Circuit PMB 2401 Preliminary Data Bipolar 1C Features • Heterodyne receiver with demodulator • Down mixing from 900 MHz receiver band to the base band • Demodulation and generation of l/Q-baseband components • Low mixer noise 10 dB SSB

Contextual Info: L M X 2 3 1 5, LM X 2320, LM X 2325 LM X2315/LM X2320/LM X2325 PLLatinum Frequency Synthesizer fo r RF PersonalCom m unications, LM X2325 2.5 GHz, LM X2320 2.0 GHz, LM X2315 1.2 GHz Te x a s In s t r u m e n t s Literature Number: SN AS101D OBSOLETE a l t Semiconductor

Contextual Info: ill# ICW0RKS Preliminary WB1225 Serial Input PLL with 2.5GHz Prescaler Figure 1 Pin Diagram Features IC W ORKS BiCMOS process 0r O SCJN NC Operating voltage 2.7V to 5.5V PWDN OSC_OUT Operating frequency: up to 2.5GHz 0p VP Lock detect feature Fout BISW v cc

Contextual Info: 14E D INTEGRATED DEVICE kitegrated DeviceTechnology, Inc «4025771 D003Ì11 7 IDT 49C410 IDT49C410A 16-BIT CMOS MICROPROGRAM SEQUENCER : MICROSLICE T-W-H-51 PRODUCT FEATURES: DESCRIPTION: • 16-bit wide address path — Address up to 65,536 words of microprogram memory

Contextual Info: 000 SDC-14610/15 SERIES ILC DATA DEVICI CORPORATION_ THREE CHANNEL 14 & 16 BIT TRACKING S/D CONVERTERS FEATURES DESCRIPTION The SDC-14610/15 Series are small low cost triple Synchro- or Resolverto-Digital Converters. The SDC-14610 Series is fixed at 14 bits, the SDC-14615

Contextual Info: IMI14 5155 / / / I I CMOS LSI SERIAL INPUT PLL FREQUENCY SYNTHESIZER I n t e r n a t io n a l M ic r o c ir c u it s I n c PRODUCT FEATURES • PRODUCT DESCRIPTION General Purpose Applications: CATV, AM/FM Radios, Scanning Receivers, 2-Way Radios, Amateur Radios, TV Tuning

Contextual Info: Preliminary WB1337X ill# ICW 0RKS Dual Serial Input PLL with 550MHz Prescalers Features Figure 1 IC W O R KS BiCMOS process Pin Diagram Operating voltage 2.7V to 5.5V v cc2 v cc1 Operating frequency to 550M H zw ith inputs of -2 5 d B m and VCC of 3.0V V P2

Contextual Info: □ DTC-19300 ILC DATA DEVICE CORPORATION_ _ _ LVDT/RVDTTO DIGITAL CONVERTER FEATURES DESCRIPTION The D TC-19300 is a 12 or 14 bit LVDT Linear Variable Differential Trans­ former or RVDT (Rotary Variable Differ­ ential Transform er) to digital converter

Contextual Info: Preliminary ill# ICW 0RKS WB1332X Dual Serial Input PLL with 1.2GHz and 510MHz Prescalers Features Figure 1 • IC WORKS BiCMOS process Pin Diagram • Operating voltage 2.7V to 5.5V — LI Vcc2 • Operating frequency to 1,2GHz and 510MHz with inputs of - 1 5dBm and Vcc of 3.0V

piezoelectric control circuit diagram

Contextual Info: UCC2975, UCC2976, UCC2977 UCC3975, UCC3976, UCC3977 SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002 MULTIĆTOPOLOGY PIEZOELECTRIC TRANSFORMER CONTROLLER FEATURES D 3-V to 13.5-V Operation D Supports Flyback UCC3975 , Half-Bridge D D D D D DESCRIPTION