V.8 BIS Search Results

TA 2119 AF

Abstract: 54HC77
Contextual Info: SN54HC77, SN74HC77 4 BIT BISTABLE LATCHES D 2 6 8 4 , DECEM BER 1 9 8 2 • Package Options Include Plastic "Sm a ll O utline" Packages, Standard Plastic and Ceram ic 300-mil DIPs SN54H C77 S N 74H C 77. R E V IS E D S E P T E M B E R 1 9 8 7 J PACKAGE D OR N P A C K A G E

Contextual Info: SN54ALS151, SN74ALS151, SN74AS151 1-0F-8 DATA SELECTORS/MULTIPLEXERS _ SDAS205A - APRIL 1982 - REVISED DECEMBER 1994 • 8-Llne to 1-Line Multiplexers Can Perform SN54ALS151 . . . j p a c k a g e SN74ALS151, SN74AS151 . . . D OR N PACKAGE crop v ie w

VAL-MS 230 ST

Abstract: FLT-35 FLASHTRAB FLT-35 FLT 350 ST PHOENIX VAL-MS230ST VAL-MS phoenix contact 28 39 33 4
Contextual Info: 9663901_PS BC-440_3_FM.fm Seite 1 Mittwoch, 29. M rz 2006 10:33 10 POWERSET BC-440/3/FM Installation Instructions POWERSET BC-440/3/FM 28 58 76 8 L-N FLT 35 CTRL-1.5 230 V AC 400 V AC UC 440 V AC 50/60 Hz 440 V AC ≤ 1,5 kV ≤ 2,2 kV 35 kA / 17,5 As / 305 kJ/Ω

Contextual Info: TELEFUNKEN LS 30 UKW -Triode Technische D aten und S tre u w e rte 1. A llg e m e in e D a te n -2 0 * H e iz s p a n n u n g .12,6 V Grenzwerte 1 0 ,8 .14.5 V H e iz s tro m .0,26 v 0,31 A

ADuM3160

Abstract: adum4160 ADuM41601
Contextual Info: FEATURES USB 2.0 compatible Low and full speed data rate: 1.5 Mbps and 12 Mbps Bidirectional communication 4.5 V to 5.5 V VBUS operation 7 mA maximum upstream supply current @ 1.5 Mbps 8 mA maximum upstream supply current @ 12 Mbps 2.3 mA maximum upstream idle current

ADuM1201 application

Abstract: adum1201brz 8 lead soic-n package R8 ADUM1201WSRZ ADUM1201ARZ
Contextual Info: Narrow body, RoHS-compliant, SOIC 8-lead package Low power operation 5 V operation 1.1 mA per channel maximum @ 0 Mbps to 2 Mbps 3.7 mA per channel maximum @ 10 Mbps 8.2 mA per channel maximum @ 25 Mbps 3 V operation 0.8 mA per channel maximum @ 0 Mbps to 2 Mbps

A1S1

Contextual Info: » Am2055 Am205s Extended PCM Interface Controller EPIC A dvanced Data Sheet M icro Revision TM 8/89 D e v ic e s . * » ' * ";> * • ,• * 9* r * « £ • • « \ • • •• A d v a n c e d M i n ':; S ' D i - y ; . - ì ->- n / Armnfltmn; 11149D/0

H8/3102

Contextual Info: Section 1. Overview 1 .1 O v e r v ie w The H8/3102 is a single-chip microcomputer built around a high-speed H8/300 CPU core. An 8-kbyte EEPROM, 16-kbyte ROM, 512-byte RAM, and 2-bit I/O port are integrated onto the H8/3102 chip. Operating at a maximum 5-MHz clock rate at 5 V, the H8/300 CPU rapidly executes bitmanipulation instructions, arithmetic and logic instructions, and data transfer instructions.

PEB2255

Abstract: irs5 PXB4219E PXB4220 PXB4220E PXB4221 PXB4221E PXB4219 TINI microcontroller cards
Contextual Info: P re li mi na ry D ata S he et , DS 1, J ul y 20 01 IW E 8 In te r wo r k i n g E le m en t f or 8 E 1/ T1 L i ne s P XB 4 2 19 E /P X B 4 22 0 E/ P X B 42 21 E V er s i o n 3. 4 Da ta c o m N e v e r s t o p t h i n k i n g . Edition 2001-07 Published by Infineon Technologies AG,

SN 5477

Contextual Info: TYPES SN5475, SN5477, SN54L75, SN54L77, SN54LS75, SN54LS77, SN7475, SN74LS75 4-BIT BISTABLE LATCHES M A R C H 1 9 7 4 - R E V IS E D D E C E M B E R 1 9 8 3 S N 5475, SN 54LS75 . . J OR W PACKAGE S N 54L75 . . . J PACKAGE S N 7475 . . . J OR N PACKAGE SN74LS75 . , . D, J OR N PACKAGE

i386 ex

Abstract: ATM machine using microcontroller PEB2255 TR-NWT-000170 alps lcd 14 pin ATM circuit diagram atm lh 108 atm over pdh irs5 MOTOROLA 4221
Contextual Info: D at a S hee t, DS 3 , M ay 2 00 2 IWE8 Interworking Element for 8 E1/T1 Lines PXB4219 / PXB4220 / PXB4221 V er s i o n 3 . 3 Datacom N e v e r s t o p t h i n k i n g . Edition 2002-05-06 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany

ASX 12 D Germanium Transistor

Abstract: 1394 audio subunit domino logic,dynamic logic ibm 6X86MX IBM-6x86MX Japan dvd cjc Transistor Data Book nand flash HET PR333 PR300 APPLE LM INVERTER
Contextual Info: v ol 4 3 ume A publication of IBM Microelectronics IBM’s Blue Logic Strategy In This Issue Third Quarter 1998, Vol. 4, No.3 1 IBM’s Blue Logic Strategy 4 High-Speed Design Styles Leverage IBM Technology Prowess 8 Low-Power Methodology and Design Techniques

Contextual Info: NEC 3.3-V olt, 0.44-M icron G ate Arrays NEC Electronics Inc. Prelim inary April 1996 Figure 1. 672-pin BGA Description NEC’s 3.3-volt QB-8 fam ily consists of ultra-highperform ance, subm icron gate arrays targeted for applications requiring high speeds and low power

Contextual Info: Advance information •■ I l AS4LC2M8S0 AS4LC1M1ÓS0 A 3.3V 2 M x 8 /lM x 16 CMOS synchronous DRAM Features Automatic and direct precharge Burst read, single write Can assert random column address in every cycle LVl'l'L compatible V O 3.3Vpower supply JEDEC standard package, pinout and function

ANSI-644

Contextual Info: 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter AD9634 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD VIN+ PIPELINE 12-BIT ADC VIN– VCM AGND DRVDD 12 D0±/D1± PARALLEL DDR LVDS AND DRIVERS AD9634 REFERENCE . . . D10±/D11± DCO± OR± 1-TO-8

ANSI-644

Abstract: AD9634
Contextual Info: 14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter ADC AD9642 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD VIN+ PIPELINE 14-BIT ADC VIN– VCM AGND DRVDD D0±/D1± 14 AD9642 PARALLEL DDR LVDS AND DRIVERS D12±/D13± DCO± REFERENCE 1-TO-8 CLOCK

Contextual Info: SK5562 DATE REV 7-ao 04 NC «-13 A 04 8-85 B OS P 0 9 T R 0 M C N D U ST R lE S BC U E V C S T lC DATA O N T rtS ORMMNG TO B E RELIABLE, SIN C E THE TECHMCAL INFORMATION IS O V E N F R EE O F CHARGE, T IC U SE R E l* L O Y S S U C H »FO RM AT IO N AT M S OWN DISCRETION

Contextual Info: A I R C H I L D e c e m b e r 1991 D . ,n , R e v is e d D e c e m b e r 199 8 D SE M CONDUCTOR TM 74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs General Description Features T h e A C T Q 1 6 5 4 3 c o n ta in s s ix te e n n o n -in v e rtin g tra n s c e iv ­

PLB12M

Contextual Info: SK5566 DATE REV 7-ao 04 NC -1 4 A 04 8-85 B OS P 0 9 T R 0 M C N D U ST R lE S BE LIE V E S T lC DATA O N T rtS ORAWMC TO B E RELIABLE, SIN C E THE TECHMCAL INFORMATION IS O V E N F R EE O F CHARGE, T IC U SE R E l* L O Y S S U C H »FO RM AT IO N AT M S OWN DISCRETION

schematic of TTL latch

Abstract: TA 8275 H signetics 8280 NT 101 8T01
Contextual Info: r signatics QUAD BISTABLE LATCH DIGITAL 8000 SER IES T T L/ M S I d e s c r ip t io n PIN C O N F IG U R A T IO N S Top View The 8 2 7 5 is a Q U A D L A T C H c irc u it d e sign e d to p ro v id e temporary storage o f fo u r b its o f in fo rm a tio n . A c o m m o n

Taiyo 88-T

Contextual Info: TANDARD PRODUCT PMC-950919 I . . . 1^1 im 1 / I V ia PMC-Sierra, Inc. ISSUE 6 P M 5 3 4 8 S /U N I-D U A L SATURN USER NETWORKINTERFAC PM5348 S/UNI-155-DUAL DUAL SATURN USER NETWORK INTERFACE 155.52 & 51.84 Mbit/s Issue 6: February 1997 PMC-Sierra, Inc. 105-8555B axter Place, Burnaby, BC Canada V5A 4V7 604.415.6000

SK6370

Abstract: sk742 SK7421
Contextual Info: SK7421 REVISION RECORD ECO 2 5 9 6 9 ECO 2 8 2 7 5 DATE REV 5-16 06 NC 8-6 07 A P O S IT R O N IC IN D U S T R IE S B E L IE V E S T H E DATA ON T H IS D RAW IN G T O B E R E L IA B L E , S IN C E T H E T E C H N IC A L IN F O R M A T IO N IS G IVEN F R E E O F C H A R G E , T H E U S E R

Contextual Info: M ITSU B IS H I M IC R O C O M P U T E R S M 3 7 1 0 2 M 8 -X X X S P /F P M 3 7 2 0 1 M 6 -X X X S P S I N G L E - C H IP 8 -B IT C M O S M I C R O C O M P U T E R for V O L T A G E S Y N T H E S I Z E R with O N - S C R E E N D I S P L A Y C O N T R O L L E R

PEB2255

Abstract: cfrp irs5 RFPP 386EX PEB20954 PXB4219 PXB4220 PXB4221 TR-NWT-000170
Contextual Info: D at a Sh e et , D S 2, 0 9. 20 00 IW E8 I n t e r w o r k i n g E le m e n t f o r 8 E 1 / T 1 Lines P X B 4 2 1 9 / PX B 4 2 2 0 / PX B 4 2 2 1 Version 3.3 Datacom N e v e r s t o p t h i n k i n g . Edition 2000-09-04 Published by Infineon Technologies AG,