US8 PACKAGE FAIRCHILD Search Results

Contextual Info: NC7WZ08 TinyLogic UHS Dual 2-Input AND Gate Features General Description • Space saving US8 surface mount package The NC7WZ08 is a dual 2-Input AND Gate from Fairchild's Ultra High Speed Series of TinyLogic. The device is fabricated with advanced CMOS technology to

Contextual Info: Revised January 2003 NC7NZ17 TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs General Description Features The NC7NZ17 is a triple buffer with Schmitt trigger inputs from Fairchild’s Ultra High Speed Series of TinyLogic in the US8 package. The device is fabricated with advanced

7NZ17

Abstract: NC7NZ17K8X
Contextual Info: Revised January 2005 NC7NZ17 TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs General Description Features The NC7NZ17 is a triple buffer with Schmitt trigger inputs from Fairchild’s Ultra High Speed Series of TinyLogic in the US8 package. The device is fabricated with advanced

MAB08A

Abstract: JEDEC MO-187 CA us8 Package FAIRCHILD JEDEC MO-187 MO-187 8-Lead US8
Contextual Info: Revised April 2002 Package MAB08A 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide Package Number MAB08A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

Contextual Info: Revised October 2002 NC7NZ17 TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs General Description Features The NC7NZ17 is a triple buffer with Schmitt trigger inputs from Fairchild’s Ultra High Speed Series of TinyLogic in the US8 package. The device is fabricated with advanced

Contextual Info: NC7NP14 TinyLogic ULP Triple Inverter with Schmitt Trigger Input Features General Description • Space saving US8 package The NC7NP14 is a triple inverter with Schmitt trigger input from Fairchild’s Ultra Low Power ULP Series of TinyLogic®. Ideal for applications where battery life is

NZ17

Abstract: nz17 mark
Contextual Info: Revised November 2005 NC7NZ17 TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs General Description Features The NC7NZ17 is a triple buffer with Schmitt trigger inputs from Fairchild’s Ultra High Speed Series of TinyLogic in the US8 package. The device is fabricated with advanced

WZ00

Abstract: J-STD-020B MAC08A MO-187 NC7WZ00 NC7WZ00K8X NC7WZ00L8X Dual 2-input NAND gate
Contextual Info: NC7WZ00 TinyLogic UHS Dual 2-Input NAND Gate Features General Description • Space saving US8 surface mount package The NC7WZ00 is a dual 2-Input NAND Gate from Fairchild's Ultra High Speed Series of TinyLogic. The device is fabricated with advanced CMOS technology to

"AND Gate"

Abstract: J-STD-020B MAC08A MO-187 NC7WZ08 NC7WZ08K8X NC7WZ08L8X
Contextual Info: NC7WZ08 TinyLogic UHS Dual 2-Input AND Gate Features General Description • Space saving US8 surface mount package The NC7WZ08 is a dual 2-Input AND Gate from Fairchild's Ultra High Speed Series of TinyLogic. The device is fabricated with advanced CMOS technology to

Contextual Info: NC7WZ00 TinyLogic UHS Dual 2-Input NAND Gate Features General Description • Space saving US8 surface mount package The NC7WZ00 is a dual 2-Input NAND Gate from Fairchild's Ultra High Speed Series of TinyLogic. The device is fabricated with advanced CMOS technology to

NC7NZ17

Abstract: NC7NZ17K8X
Contextual Info: Revised July 2001 NC7NZ17 TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs General Description Features The NC7NZ17 is a triple buffer with Schmitt trigger inputs from Fairchild’s Ultra High Speed Series of TinyLogic in the US8 package. The device is fabricated with advanced

U4 Package

Abstract: nz17 J-STD-020B MAC08A MO-187 NC7NZ17 NC7NZ17K8X NC7NZ17L8X
Contextual Info: Revised November 2005 NC7NZ17 TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs General Description Features The NC7NZ17 is a triple buffer with Schmitt trigger inputs from Fairchild’s Ultra High Speed Series of TinyLogic in the US8 package. The device is fabricated with advanced

Contextual Info: Revised November 2005 NC7NZ17 TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs General Description Features The NC7NZ17 is a triple buffer with Schmitt trigger inputs from Fairchild’s Ultra High Speed Series of TinyLogic in the US8 package. The device is fabricated with advanced

Contextual Info: NC7WZ00 TinyLogic UHS Dual 2-Input NAND Gate Features General Description • Space saving US8 surface mount package The NC7WZ00 is a dual 2-Input NAND Gate from Fairchild's Ultra High Speed Series of TinyLogic. The device is fabricated with advanced CMOS technology to

J-STD-020B

Abstract: MAC08A MO-187 NC7NP14 NC7NP14K8X NC7NP14L8X
Contextual Info: NC7NP14 TinyLogic ULP Triple Inverter with Schmitt Trigger Input Features General Description • Space saving US8 package The NC7NP14 is a triple inverter with Schmitt trigger input from Fairchild’s Ultra Low Power ULP Series of TinyLogic®. Ideal for applications where battery life is

J-STD-020B

Abstract: MAC08A MO-187 NC7WZ08 NC7WZ08K8X NC7WZ08L8X
Contextual Info: NC7WZ08 TinyLogic UHS Dual 2-Input AND Gate Features General Description • Space saving US8 surface mount package The NC7WZ08 is a dual 2-Input AND Gate from Fairchild's Ultra High Speed Series of TinyLogic. The device is fabricated with advanced CMOS technology to

Contextual Info: Revised April 2004 NC7NZ17 TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs General Description Features The NC7NZ17 is a triple buffer with Schmitt trigger inputs from Fairchild’s Ultra High Speed Series of TinyLogic in the US8 package. The device is fabricated with advanced

7NZ17

Abstract: MO-187 NC7NZ17 NC7NZ17K8X
Contextual Info: Revised February 2002 NC7NZ17 TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs General Description Features The NC7NZ17 is a triple buffer with Schmitt trigger inputs from Fairchild’s Ultra High Speed Series of TinyLogic in the US8 package. The device is fabricated with advanced

7NZ17

Abstract: MAC08A MO-187 NC7NZ17 NC7NZ17K8X NC7NZ17L8X us8 Package
Contextual Info: Revised April 2003 NC7NZ17 TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs General Description Features The NC7NZ17 is a triple buffer with Schmitt trigger inputs from Fairchild’s Ultra High Speed Series of TinyLogic in the US8 package. The device is fabricated with advanced

XOR schmitt trigger

Abstract: 3-input-XOR ttl XOR gate circuit "XOR Gate" 74 XOR GATE U04 fairchild xor ttl 74 and logic gate data sheet for 3 input xor gate dual schmitt-trigger inverters
Contextual Info: TinyLogic for Portables: Saving Space.Saving Power over 60 logic functions in six package types and five performance levels ULP: low noise @ low Vcc HS: high speed/low noise HST: high speed/TTL inputs ULP: 50% lower power see table Available in US8, SC70 and the NEW MicroPak Package

Contextual Info: NC7SV74 TinyLogic ULP-A D-Type Flip-Flop with Preset and Clear Features • • • • • General Description Space-saving US8 surface-mount package MicroPak Pb-free leadless package 0.9V to 3.6V VCC supply operation 3.6V over-voltage tolerant I/Os at VCC from 0.9V to 3.6V

NC7SZ74K8X

Abstract: NC7SZ74 MO-187
Contextual Info: Revised February 2002 NC7SZ74 TinyLogic UHS D-Type Flip-Flop with Preset and Clear General Description Features The NC7SZ74 is a single D-type CMOS Flip-Flop with preset and clear from Fairchild’s Ultra High Speed Series of TinyLogic in the space saving US8 package. The device

Contextual Info: Revised November 2005 NC7NZ34 TinyLogic UHS Triple Buffer General Description Features The NC7NZ34 is a triple buffer from Fairchild’s Ultra High Speed Series of TinyLogic in the space saving US8 package. The device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive

Contextual Info: NC7WZ132 TinyLogic UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs Features General Description • Space saving US8 surface mount package The NC7WZ132 is a dual 2-Input NAND Gate from Fairchild's Ultra High Speed Series of TinyLogic®. The device is fabricated with advanced CMOS technology to