UDB 12 Search Results

ramp

Contextual Info: Up-Down Ramp Buffer ADTECH Analog-Digital Technology, Inc. Model No. UDB 97 The Adtech Model UDB 97 Up-Down Ramp Buffer provides an accurate and economical means of supervisory process control. A contact state change or pulse input drives the standard output process signal to ramp up

STP1080A

Abstract: IEEE1149
Contextual Info: STP1080A July 1997 UltraSPARC -I Data Buffer UDB-I DATA SHEET Companion Device for 167/200 MHz UltraSPARC-I Systems DESCRIPTION The UDB-I is a data buffer device used in UltraSPARC-I systems to connect the CPU and its external SRAM cache bus to the system bus:

STP1081

Abstract: 75193 Sun UltraSparc T2 40N20
Contextual Info: STP1081 July 1997 UltraSPARC -II Data Buffer UDB-II DATA SHEET Companion Device for 250/300 MHz UltraSPARC-II Systems DESCRIPTION The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II microprocessor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the

Contextual Info: S un M icroelectronics O c to b e r 1996 UltraSPARC -!! Data Buffer UDB-II DATA SHEET High-Capacity, Two-Speed Data Transfer D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical integrated circuit microchips connecting the UltraSPARC-II microprocessor and its E-Cache to the slower system data bus. These

Contextual Info: STP1080A S un M ic r o e l e c t r o n ic s J u ly 1997 UltraSPARC -! Data Buffer UDB-I DATA SHEET Companion Device for 167/200 MHz UltraSPARC-I Systems D e s c r ip t io n The UDB-I is a data buffer device used in UltraSPARC-1 system s to connect the CPU and its external SRAM

STP1080

Abstract: ultrasparc 3
Contextual Info: UltraSPARC -! Data Buffer UDB-I DATA SHEET Companion Device for 167/200 MHz UltraSPARC-1 Systems D e s c r ip t io n The UDB-I is a data buffer device used in UltraSPARC-1 system s to connect the CPU and its external SRAM cache bus to the system bus: • On the C P U /SR A M side, the E-Cache Bus consists of 128 data bits and 16 parity bits

ultrasparc

Contextual Info: UltraSPARC “-!! Data Buffer UDB-II DATA SHEET Companion Device for 250/300 MHz UltraSPARC-II Systems D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II micro­ processor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the

Contextual Info: S un M icroelectronics O c to b e r 1996 UltraSPARC -!! Data Buffer UDB-II DATA SHEET High-Capacity, Two-Speed Data Transfer D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical integrated circuit microchips connecting the UltraSPARC-II microprocessor and its E-Cache to the slower system data bus. These

J1039

Contextual Info: 1300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com Universal Development Board Reference Manual Revised January 15, 2014 This manual applies to the UDB rev. E Table of Contents Table of Contents . 1

Contextual Info: High Voltage Doorbell Modules Standard and Fast Recovery UDA, UDB, UPC, UDD, UDE & UDF Series Dim. Inches Millimeter Minimum Maximum Minimum Maximum Notes A B C D E 0.63 -0.25 - - 16.08 -Dia. 19.81 48.26 Dia. -Typ. - 1 / 4 - 2 8

Contextual Info: High Voltage Doorbell Modules Standard and Fast Recovery UDA, UDB, UPC, UDD, UDE & UDF Seriesl Dim. Inches Millimeter Minimum Maxim um Minimum Maxim um Notes A B C D E 0.63 -0.25 - -0.78 1.90 - 16.08 -Dia. 19.81 48.26 Dia. -Typ.

Contextual Info: PSoC Creator Component Datasheet SMBus and PMBus Slave 2.0 Features • SMBus Slave mode • PMBus Slave mode  SMBALERT# pin support  25 ms Timeout  Fixed Function FF and UDB implementations  Configurable SM/PM Bus commands General Description

Contextual Info: PSoC Creator Component Datasheet SM Bus and PM Bus Slave 2.10 Features • SMBus Slave mode • PMBus Slave mode  SMBALERT# pin support  25 ms Timeout  Fixed Function FF and UDB implementations  Configurable SM/PM Bus commands General Description

MCE-100

Abstract: STP1081 STP5211UPA-250 MC100LVE111 MC100LVE210
Contextual Info: STP5211 July 1997 UltraSPARC -II CPU Module DATA SHEET Complete 248 MHz CPU, 1.0 MB E-Cache, UDB-II DESCRIPTION The UltraSPARC-II module is a high performance, SPARC V9 compliant, small form factor processor module. It interfaces to the UltraSPARC Port Architecture UPA interconnect bus.

MS51830

Abstract: NAS1394 NAS1395 MS51830-201L NAS1394C3L MS51830-202 ms51830-201 NAS1394C3 MS51831-102 m6 bolt shear strength
Contextual Info: UniSert Kit Assortments Repair Kits UniSert Kit Assortments Convenient UniSert Kits − the right Insert and the correct Installation Tool for your repairs. UNITED INSERTS INCLUDED IN KIT KIT NO. ID UNITED THD PART NO. UNF FINE KIT QTY UDB-1-US-F TOOLS INCLUDED

doorbell circuit working

Abstract: UDA-10 UDA-15 UDC-10 UDC-15 7.5kv diode 5KV fast recovery DIODE
Contextual Info: RECTIFIER ASSEMBLIES UDA, UDB, UDC, UDD , UDE, UDF SERIES High Voltage Doorbell Modules, Standard and Fast Recovery FEATURES DESCRIPTION • • • • • • • This series of high-voltage, high-current stacks that incorporate a unique modular design makes it ideally suited for high

unitrode UDB5

Abstract: unitrode stackable rectifier doorbell 6V unitrode udb UDA-10 UDA-15 UDC-10 UDC-15 doorbell circuit working UDF5
Contextual Info: UDA, UDB, UDC, UDD , UDE, UDF SERIES RECTIFIER ASSEMBLIES High Voltage Doorbell Modules, Standard and Fast Recovery FEATURES DESCRIPTION • • • • • • • This series of high-voltage, high-current stacks that incorporate a unique modular design makes it ideally suited for high

Contextual Info: Ultra Deep Blue 180° Angle Ceramic Chip CR 50 UDB Features Solid State Ceramic Chip High Power Thermal Absorbtion Superior Light Uniformity Over 180º End−to−End and Side−to Side Stackable to a pitch of 1.3mm Solderpads confirm to Mil−Std 883B Caution: Static electricity and surge damages blue LED chip

in138

Abstract: SPARC v9 architecture BLOCK DIAGRAM cpu lga UltraSPARC ii
Contextual Info: S un M icro electro nics July 1997 UltraSPARC -!! CPU Module DATA SHEET Complete 296 MHz CPU, 2.0 MB E-Cache, UDB-II D e s c r ip t io n The UltraSPARC-II module is a high performance, SPARC V9 compliant, small form factor processor module. It interfaces to the UltraSPARC Port Architecture UPA interconnect bus.

Contextual Info: STP5211 S un M ic r o e l e c t r o n ic s J u ly 1997 UltraSPARC -!! CPU Module DATA SHEET Complete 248 MHz CPU, 1.0 MB E-Cache, UDB-II D e s c r ip t io n The UltraSPARC-II m odule is a high perform ance, SPARC V9 com pliant, small form factor processor module.

Contextual Info: STP5212 S un M ic r o e l e c t r o n ic s J u ly 1997 UltraSPARC -!! CPU Module DATA SHEET Complete 296 MHz CPU, 2.0 MB E-Cache, UDB-II D e s c r ip t io n The UltraSPARC-II m odule is a high perform ance, SPARC V9 com pliant, small form factor processor module.

Contextual Info: PSoC Creator コンポーネントデータシート SMBus/ PMBus スレーブ 1.0 特長 • SMBus スレーブモード • PMBus スレーブモード  SMBALERT#ピンをサポート  25ms のタイムアウト  専用機能ブロック Fixed-function: FF 実装と UDB 実装

Contextual Info: 〖 中 易 电 测 〗 页码，1/1 UDA UDA 、UDB系列高精度称重传感器 UDB 系列高精度称重传感器 型号：UDA、UDB系列高精度称重传感器 价格：－－－ －－－ 【性能特点】 ◇ 高精度，长期稳定性好 ◇ 高灵敏度及阻抗输出

Contextual Info: PSoC Creator 器件基本介绍 SMBus 和 PMBus 从器件 1.0 特性 • SMBus 从器件模式 • PMBus 从器件模式  SMBALERT# 引脚支持  25 ms 超时  固定功能 FF 和 UDB 实现  可配置 SM/PM 总线命令 概述 系统管理总线 (SMBus) 和电源管理总线 (PMBus) 从器件组件提供了一种简单的方式来使用其上运