UAS 111 Search Results

rxied1

Abstract: RXIED Z16C32 AD10 AD11 AD12 AD14 SL1660 rxc 151
Contextual Info: PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION 1 Z16C32 SL1660 ONLY 1 IUSC INTEGRATED UNIVERSAL SERIAL CONTROLLER GENERAL DESCRIPTION The IUSC Integrated Universal Serial Controller is a single-channel multple protocol data communications device with on-chip dual-channel DMA. The integration of a highspeed serial communications channel with a high performance DMA facilitates higher data throughput than is possible with discrete serial/DMA chip combinations. The buffer chaining capabilities combined with features like

DB25-ISO

Abstract: ss7 gsm PCM31 DTE dce X21 RX-2 1111 DB15-ISO PCM-31 RS-449 SCSI-36 PCM30
Contextual Info: Анализатор параметров сигналов ИКМ и передачи данных SunSet E20 ОСНОВНЫЕ ВОЗМОЖНОСТИ • • • • • • • • • • • • • • • • • Измерения первичного цифрового потока 2 Мбит/с: анализ по G.821, G.826,

uas 111

Abstract: AD10 AD11 AD12 AD14 DC3012 Z16C35
Contextual Info: — C'iARCOM D C 3 0 1 2 DOCUMENT CONTROL— .IAS TER C u s t o m e r Pr o c u r e m e n t S p e c if ic a tio n < £ Z iI ß Ö Z16C35 CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER GENERAL DESCRIPTION The Z16C35ISCC is a CMOS superintegrated device with

Z16C32

Contextual Info: P r e l im in a r y C u s t o m e r P r o c u r e m e n t S p e c if ic a t io n Z16C32 SL1660 O nly . TM IU S C In t e g r a t e d U n iv e r s a l S e r ia l C o n t r o l l e r GENERAL DESCRIPTION The IUSC Integrated Universal Serial Controller is a sin­

mc68440

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC68450 Technical Sum m ary Direct Memory Access Controller M68000 microprocessors utilize state-of-the-art MOS technology to maximize performance and throughput. The MC68450 direct memory access controller DMAC is designed to complement the performance and architectural capa­

transistor marking WR5 72

Abstract: txc xtal sdlc ibm signals z8030 DDR14
Contextual Info: < 2 > 2 iL G E Pr o d u c t S p é c if ic a t io n Z16C35/Z85C35 CMOS ISC C INTEGRATED SERIAL C o m m u n ic a t io n s C o n t r o l l e r FEATURES • Two general-purpose SCC channels, four DMA channel; and a Universal Bus Interface Unit. ■ Software compatible to the Zilog CMOS SCC

DTC in UDS

Abstract: MC68230 MC68440 Motorola MC68230 LSHA mc68450 74LS245 74LS373 M68000 MC68008
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC68440 Technical Sum m ary Dual-Channel Direct Memory Access Controller M68000 microprocessors utilize state-of-the-art MOS technology to maximize performance and throughput. The MC68440 dual-channel direct memory access

Contextual Info: P r o d u c t S pecification < £ 3 L0 E Z16C35/Z85C35 CMOS I SCC INTEGRATED SERIAL C o m m u n ic a t io n s C o n t r o lle r FEATURES • Two General-Purpose SCC Channels, Four DMA Channel; and a Universal Bus Interface Unit. ■ Software Compatible to the Zilog CMOS SCC

Contextual Info: Pr elim in a ry Pro d u ct Sp ec ifica tio n < £ Z iIí3 G Z16C35 CMOS IS C C I n t e g r a t e d S e r ia l C o m m u n ic a t io n s c o n t r o l l e r FEATURES Supports all Zilog CMOS SCC features: • Low power CMOS technology ■ Two g e n e ra l-p u rp o s e SCC channels, four DMA

Contextual Info: P r e lim in a r y P r o d u c t S p e c if ic a t io n < £ Z iIÍ3 G Z16C35 CMOS ISCC In t e g r a t e d S e r ia l COMMUNICATIONS CONTROLLER FEATURES Supports all Zilog CMOS SCC features: • Low power CMOS technology ■ Two general-purpose SCC channels, four DMA

z16c35

Contextual Info: < £ 2 iL Œ 3 P r o d u c t S p e c if ic a t io n Z16C35/Z85C35 CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER FEATURES • Two G eneral-Purpose SCC Channels, Four DMA Channel; and a Universal Bus Interface Unit. ■ Software Com patible to the Zilog CMOS SCC

Contextual Info: Agilent N2X SIP Protocol Emulation Software N5588A Technical Data Sheet The most comprehensive tool for realistic and high scale testing of SIP-enabled devices such as BNGs, B-RASs, and edge routers. N5588A - SIP Protocol Emulation Software Key Features • High scale testing – emulation of

Contextual Info: ÉÈÉâ ^ MARCOM DC2 5 1 5 DOCUMENT CONTROL_ MASTER PRODUCT SPECIFICATION Z16C35 # # CMOS IS C C I nteg r a ted S er ia l C o m m u n ic a t io n s C o n tr o lle r PRODUCT SPECIFICATION Z16C35 CMOS IS C C I n t e g r a t e d S e r ia l C o m m u n ic a t io n s C o n t r o l l e r

Contextual Info: DS2282 PRELIMINARY DS2282 DALLAS SEMICONDUCTOR T1 FDL CONTROLLER/ MONITOR Stik FEATURES Stik LAYOUT • Fully implements the FDL message format as described in TR-TSY-000194 and T1.403-1989 • Supports both Scheduled Performance Report Messages and Unscheduled Messages

AD0-AD15

Abstract: AD11 AD12 CRC-16 Z16C35 CSA-1V sdlc ibm signals
Contextual Info: ÉÈÉâ ^ MARCOM D C 2515 DOCUMENT CONTROL, MASTER PRODUCT SPECIFICATION Z16C35 CMOS ISCC # # I nteg r a ted S er ia l C o m m u n ic a t io n s C o n tr o lle r PRODUCT SPECIFICATION Z16C35 CMOS IS C C I n tegrated S e r ia l C o m m u n ic a t io n s C o n t r o l l e r

hd68000

Contextual Info: -U172.1 HD63450, HD63450Y, HD63450P HD63450PS, HD63450CP Ci CMOS Direct Memory Access Controller SEPTEMBER, 1989 0 H IT A C H I The HD63450 is a CMOS Direct Memory Access Controller DMAC . It is upwardly compatible with the NMOS DMAC HD68450. In addition to the NMOS DMAC HD68450 features, the

Bi-phase-M Coding

Abstract: 16C32 Z16C32 TTC 103 AD10 AD11 AD12 AD14 16c3220
Contextual Info: P R E L I M I N A R Y ZILOG Z16C32 IUSC PRELIMINARY PRODUCT SPECIFICATION Z16C32 IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER FEATURES • Two Full-Capacity 20 MHz DMA Channels, Each with 32-Bit Addressing and 16-Bit Data Transfers. ■ DMA Modes Include Single Buffer, Pipelined, ArrayChained and Linked-Array Chained.

Z16C32

Contextual Info: P R E L I M I N A R Y ZILOG Z16C32 IUSC PRELIMINARY PRODUCT SPECIFICATION Z16C32 IUSC™ I NTEGRATED UNIVERSAL SERIAL CONTROLLER FEATURES • Two Full-Capacity 20 MHz DMA Channels, Each with 32-Bit Addressing and 16-Bit Data Transfers. ■ DMA Modes Include Single Buffer, Pipelined, ArrayChained and Linked-Array Chained.

8287 INTEL

Abstract: Z16C32 AD10 AD11 AD12 AD14
Contextual Info: P R E L I M I N A R Y ZILOG Z16C32 IUSC PRELIMINARY PRODUCT SPECIFICATION Z16C32 IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER FEATURES • Two Full-Capacity 20 MHz DMA Channels, Each with 32-Bit Addressing and 16-Bit Data Transfers. ■ DMA Modes Include Single Buffer, Pipelined, ArrayChained and Linked-Array Chained.

Contextual Info: SIEM ENS 1M X 9-Bit Dynamic RAM Module HYM 91000S/L-60/-70/-80 HYM 91000SL/LL-60/-70 Advanced Information • 1 048 576 words by 9-bit organization • Fast access and cycle 60 ns access time 110 ns cycle time -60 70 ns access time 130 ns cycle time (-70

Z16C32

Contextual Info: P r e l im in a r y P r o d u c t S p e c if ic a t io n Z16C32 IUSC INTEGRATED UNIVERSAL SERIAL CONTROLLER FEATURES • Two full-capacity 20 MHz DMA Channels each with 32-bit addressing and 16-bit data transfers. ■ DMA Modes include single buffer, pipelined, arraychained and linked-array chained.

Contextual Info: Preliminary Product Specification < ^ Z iI ß G Z16C31 IUSC INTEGRATED UNIVERSAL S e r ia l C o n t r o l le r FEATURES • Two full-capacity 20 MHz DMA Channels with Bus Master Control, each with 32-bit addressing and 16-bit data transfers. ■ DMA M odes include single block, buffered, arraychained and linked-array chained.

Contextual Info: NN5283206 series CMOS 8Mbit 131,072 wordsx32bitsx2 banks Synchronous Graphic RAM Preliminary Specification DESCRIPTION This product is a CMOS Synchronous Graphic Random Access Memory (SGRAM) organized as 131,072 words x 32 bits x 2 banks. This product features a fully synchronous operation referenced to a positive edge of clock input. The read / write

MC68442

Abstract: MC6844
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC68440 MC68442 Technical Sum m ary Dual-Channel Direct Mem ory Access Controllers M 68000 m ic ro p ro c e s s o rs u tilize sta te -o f-th e -a rt M O S te c h n o lo g y to m a x im iz e p e rfo rm a n c e and th ro u g h p u t. The M C 68440 d ua l-ch a n n e l d ire c t m e m o ry access c o n tro lle r D D M A is d e s ig n e d to