TZX 16 C Search Results

TZX18B

Abstract: TZX 16 C
Contextual Info: TZX._ Vishay Telefunken Silicon Epitaxial Planar Z-Diodes Features • Very sharp reverse characteristic • Low reverse current level • Very high stability • Low noise • Available with tighter tolerances Applications Voltage stabilization

btzx15

Abstract: TZX12B tzx6v8b
Contextual Info: Tem ic Semiconductors Silicon Epitaxial Planar Z-Diodes Features • • • • • Very sharp reverse characteristic Low reverse current level Very high stability Low noise Available with tighter tolerances Applications 94 9367 Voltage stabilization Absolute Maximum Ratings

TZX33

Abstract: Telefunken tk 19 TZX10 TZX11 TZX12 TZX13 TZX14 TZX15 TZX16 TZX18
Contextual Info: TZX. Silicon Epitaxial Planar Z–Diodes Features D D D D D Very sharp reverse characteristic Low reverse current level Very high stability Low noise Available with tighter tolerances Applications 94 9367 Voltage stabilization Absolute Maximum Ratings Tj = 25_C

Contextual Info: _ TZX. Vishay Telefunken Silicon Epitaxial Planar Z-Diodes Features • Very sharp reverse characteristic • Low reverse current level • Very high stability • Low noise • Available with tighter tolerances ^1# Applications 94 9367 Voltage stabilization

TZX24X

Abstract: TZX27B TZX10A TZX10B TZX10C TZX10D TZX11A TZX11B TZX11C TZX11D
Contextual Info: TZX. Vishay Semiconductors Silicon Epitaxial Planar Z–Diodes Features D Very sharp reverse characteristic D Low reverse current level D Very high stability D Low noise D Available with tighter tolerances Applications 94 9367 Voltage stabilization Order Instruction

TZX27B

Abstract: TZX10A TZX10B TZX10C TZX10D TZX11A TZX11B TZX11C TZX11D TZX12A
Contextual Info: TZX. Vishay Semiconductors Silicon Epitaxial Planar Z–Diodes Features D Very sharp reverse characteristic D Low reverse current level D Very high stability D Low noise D Available with tighter tolerances Applications 94 9367 Voltage stabilization Order Instruction

9607

Contextual Info: TZX. Vishay Telefunken Silicon Epitaxial Planar Z–Diodes Features D D D D D Very sharp reverse characteristic Low reverse current level Very high stability Low noise Available with tighter tolerances Applications 94 9367 Voltage stabilization Absolute Maximum Ratings

TZX 214 transistor

Abstract: 7480 full adder 1 bit MAX4967 EP1S60 SSTL-18
Contextual Info: 4. DC & Switching Characteristics S51004-3.4 Stratix devices are offered in both commercial and industrial grades. Industrial devices are offered in -6 and -7 speed grades and commercial devices are offered in -5 fastest , -6, -7, and -8 speed grades. This section

7274ns

Abstract: HC1S60 SSTL-18 TZX. Series
Contextual Info: 4. Operating Conditions H51005-3.4 Recommended Operating Conditions Tables 4–1 through 4–3 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for 1.5-V HardCopy Stratix® devices.

HC1S60

Abstract: SSTL-18 7274ns
Contextual Info: 12. Operating Conditions H51005-3.3 Recommended Operating Conditions Tables 12–1 through 12–3 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for 1.5-V HardCopy Stratix® devices.

Stratix 8300

Abstract: 484-pin BGA 4008 adders EP1S60
Contextual Info: Stratix December 2002, ver. 3.0 Introduction Preliminary Information Features. Data Sheet The StratixTM family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 114,140 logic elements LEs and up to 10 Mbits of RAM. Stratix devices offer up to 28 digital signal

logic diagram to setup adder and subtractor

Abstract: AMPP biasing circuit circuit diagram of inverting adder CMOS Logic Family Specifications logic family specification programmable logic controller timers application EP1S60
Contextual Info: Stratix February 2002, ver. 1.0 Introduction Preliminary Information Features. Data Sheet The Stratix family of programmable logic devices PLDs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 114,140 logic elements (LEs) and up to 10 Mbits of RAM. Stratix devices

diode jd 4.7-16

Abstract: MA4001
Contextual Info: Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V1-1.2 Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

CY7C344B-15HC

Abstract: CY7C344B-15PC 74HC CY7C344B C344B
Contextual Info: CY7C344B 32-Macrocell MAX EPLD Features densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344B LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two

74HC

Abstract: CY7C344B
Contextual Info: 44B CY7C344B 32-Macrocell MAX EPLD Features densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344B LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two

CY7C343B

Abstract: c343b cy7c343b-25hc
Contextual Info: CY7C343B 64-Macrocell MAX EPLD Features The CY7C343B contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks LABs connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one that

CY7C343B

Contextual Info: 43B CY7C343B 64-Macrocell MAX EPLD Features The CY7C343B contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks LABs connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one

TZX 214 transistor

Abstract: EP1S60
Contextual Info: Section I. Stratix Device Family Data Sheet This section provides the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power

CY7C343B

Contextual Info: 43B CY7C343B 64-Macrocell MAX EPLD Features The CY7C343B contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks LABs connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one

7C342B

Abstract: 68-PIN CY7C342B k941
Contextual Info: 7C342B:11/91 Revision: July 19, 2000 CY7C342B 128-Macrocell MAX EPLD Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB.

circuit diagram of inverting adder

Abstract: EP1S60 S51005-2 PN 0506
Contextual Info: Section I. Stratix Device Family Data Sheet This section provides the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power

CY7C342B-25jc

Abstract: 68-PIN CY7C342B K941
Contextual Info: CY7C342B 128-Macrocell MAX EPLD Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. • • • •

68-PIN

Abstract: CY7C342B
Contextual Info: 42B CY7C342B 128-Macrocell MAX EPLD Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. • • •

EP1S60

Abstract: "Single-Port RAM"
Contextual Info: Chapter 1. Introduction S51001-3.1 Introduction The Stratix family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities of up to 79,040 logic elements LEs and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal