TTL MANUAL Search Results
TTL MANUAL Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
|---|---|---|---|---|---|
| 54F151LM/B |
|
54F151 - Multiplexer, 1-Func, 8 Line Input, TTL |
|
||
| 93L422ADM/B |
|
93L422A - 256 x 4 TTL SRAM |
|
||
| 27S185DM/B |
|
27S185 - OTP ROM, 2KX4, 55ns, TTL, CDIP18 |
|
||
| 5962-8672601EA |
|
Parity Generator/Checker, S Series, 12-Bit, Inverted Output, TTL - Dual marked (93S48/BEA) |
|
||
| 93425ADM/B |
|
93425 - 1K X 1 TTL SRAM |
|
TTL MANUAL Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
HLT28
Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D
|
Original |
MC10ELT28, MC100ELT28 HLT28 KLT28 MC10ELT28/D HLT28 HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D | |
HLT28
Abstract: KLT28 MC100 MC100ELT28 MC10ELT28 transistor k 4110
|
Original |
MC10ELT28, MC100ELT28 HLT28 KLT28 MC10ELT28/D HLT28 KLT28 MC100 MC100ELT28 MC10ELT28 transistor k 4110 | |
HLT28
Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28
|
Original |
MC10ELT28, MC100ELT28 HLT28 KLT28 MC10ELT28/D HLT28 HT28 KLT28 KT28 MC100ELT28 MC10ELT28 | |
|
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading |
Original |
MC10ELT28, MC100ELT28 HLT28 KLT28 MC10ELT28/D | |
FT232R
Abstract: FT232RQ TTL232R-3V3 ft232r MAX232 MAX232 TTL232R TTL-232R TTL-232R-3V3 UART TTL buffer serial port to ttl using max232
|
Original |
TTL-232R TTL-232R FT232RQ FT232R TTL232R-3V3 ft232r MAX232 MAX232 TTL232R TTL-232R-3V3 UART TTL buffer serial port to ttl using max232 | |
max232 rts cts
Abstract: TTL-232R-3V3 cmos 3v3 TTL232R-3V3 FT232RQ FT232R USB UART ttl drive USB CABLE MAX232 for level converter notes on serial communication MAX232
|
Original |
TTL-232R-3V3 TTL-232R-3V3 FT232RQ FT232R max232 rts cts cmos 3v3 TTL232R-3V3 FT232R USB UART ttl drive USB CABLE MAX232 for level converter notes on serial communication MAX232 | |
MC10H605-D
Abstract: MC100H605 MC10H605 MC10H605FN
|
Original |
MC10H605, MC100H605 MC10/100H605 MC10H605/D MC10H605-D MC100H605 MC10H605 MC10H605FN | |
k 3555
Abstract: H607 MC100H607 MC10H607 MC10H607FN
|
Original |
MC10H607, MC100H607 MC10H/100H607 10HTM MC10H607/D k 3555 H607 MC100H607 MC10H607 MC10H607FN | |
MC100H605
Abstract: MC10H605 MC10H605FN
|
Original |
MC10H605, MC100H605 MC10/100H605 MC10H605/D MC100H605 MC10H605 MC10H605FN | |
MC100H605
Abstract: MC10H605 MC10H605FN SOCKET PLCC28
|
Original |
MC10H605, MC100H605 MC10/100H605 MC10H605/D MC100H605 MC10H605 MC10H605FN SOCKET PLCC28 | |
|
Contextual Info: MC10H607, MC100H607 Registered Hex PECL to TTL Translator Description The MC10H/100H607 is a 6−bit, registered PECL to TTL translator. The device features differential PECL inputs for both data and clock. The TTL outputs feature 48 mA sink, 24 mA source drive |
Original |
MC10H607, MC100H607 MC10H/100H607 MC10H607/D | |
|
Contextual Info: MC10H605, MC100H605 Registered Hex ECL to TTL Translator Description The MC10/100H605 is a 6−bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs feature balanced 24 mA sink/source |
Original |
MC10H605, MC100H605 MC10/100H605 MC10H605/D | |
marking code diode wl
Abstract: motorola ECL k 3555 PLCC-28 H607 MC100H607 MC10H607 MC10H607FN
|
Original |
MC10H607, MC100H607 MC10H/100H607 10HTM MC10H607/D marking code diode wl motorola ECL k 3555 PLCC-28 H607 MC100H607 MC10H607 MC10H607FN | |
H604
Abstract: MC100H604 MC10H604 MC10H604FN
|
Original |
MC10H604, MC100H604 MC10H/100H604 MC10H604/D H604 MC100H604 MC10H604 MC10H604FN | |
|
|
|||
|
Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock |
Original |
MC10H604, MC100H604 MC10H/100H604 MC10H604/D | |
PLCC-28
Abstract: H604 MC100H604 MC10H604 MC10H604FN
|
Original |
MC10H604, MC100H604 MC10H/100H604 MC10H604/D PLCC-28 H604 MC100H604 MC10H604 MC10H604FN | |
|
Contextual Info: Processor Interface Components—QSpan User Manual 4 Signals and DC Characteristics 4.1 Terminology The abbreviations used in this chapter are defined below. Two-state output Tristate output Bidirectional Input Output Open Drain Input with TTL threshold TTL Schmitt trigger input |
OCR Scan |
A117I 208-Pin | |
NEC C51A
Abstract: nec inverter schematic F074 marking B007 marking B003 JH-04 UPB6101C
|
OCR Scan |
iMH752S uPB6100 uPB6101 uPB6102 uPB6103 b457S55 /PB610 //PB6100 AIPB6101 AiPB6102 NEC C51A nec inverter schematic F074 marking B007 marking B003 JH-04 UPB6101C | |
JESD22-A114-A
Abstract: JESD78
|
Original |
NLU1GT50 NLU1GT50 517AA 613AD 613AE 613AF NLU1GT50/D JESD22-A114-A JESD78 | |
|
Contextual Info: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL−Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high−speed non−inverting buffer in ultra−small footprint. The device input is compatible with TTL−type input thresholds and the output has a full 5.0 V CMOS level output swing. |
Original |
NLU1GT50 NLU1GT50 613AD 613AE 613AF 517BX 517AQ NLU1GT50/D | |
MC100H680
Abstract: MC10H680 T101
|
Original |
MC10H680, MC100H680 MC10H/100H680 MC10H680/D MC100H680 MC10H680 T101 | |
ttl 7709
Abstract: MC100H680 MC10H680 T101
|
Original |
MC10H680, MC100H680 MC10H/100H680 MC10H680/D ttl 7709 MC100H680 MC10H680 T101 | |
|
Contextual Info: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL−Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high−speed non−inverting buffer in ultra−small footprint. The device input is compatible with TTL−type input thresholds and the output has a full 5.0 V CMOS level output swing. |
Original |
NLU1GT50 517AA NLU1GT50/D | |
|
Contextual Info: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL−Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high−speed non−inverting buffer in ultra−small footprint. The device input is compatible with TTL−type input thresholds and the output has a full 5.0 V CMOS level output swing. |
Original |
NLU1GT50 517AA NLU1GT50/D | |