TTL LVDS Search Results

HLT28

Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

vxis

Contextual Info: VX3311 Product Specification LVDS 21-bit Channel Link Receiver-85MHz DESCRIPTION ABSOLUTE MAXIMUM RATINGS The VX3311 receiver converts the four LVDS data s treams back into 21 bits of CMOS/TTL data. n n n n Supply voltage CMOS/TTL input voltage CMOS/TTL output voltage

KLT28

Abstract: HLT28 HT28 KT28 MC100ELT28 MC10ELT28 transistor k 4110
Contextual Info: MC10ELT28, MC100ELT28 5V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are

klt28

Abstract: MC10ELT28 HLT28
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are

MC10H605-D

Abstract: MC100H605 MC10H605 MC10H605FN
Contextual Info: MC10H605, MC100H605 Registered Hex ECL to TTL Translator Description The MC10/100H605 is a 6−bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs feature balanced 24 mA sink/source

marking code diode wl

Abstract: motorola ECL k 3555 PLCC-28 H607 MC100H607 MC10H607 MC10H607FN
Contextual Info: MC10H607, MC100H607 Registered Hex PECL to TTL Translator Description The MC10H/100H607 is a 6−bit, registered PECL to TTL translator. The device features differential PECL inputs for both data and clock. The TTL outputs feature 48 mA sink, 24 mA source drive

PLCC-28

Abstract: H604 MC100H604 MC10H604 MC10H604FN
Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock

MC100H680

Abstract: MC10H680 T101
Contextual Info: MC10H680, MC100H680 4−Bit Differential ECL Bus to TTL Bus Transceiver Description The MC10H/100H680 is a dual supply 4−bit differential ECL bus to TTL bus transceiver. It is designed to allow the system designer to no longer be limited in bus speed associated with standard TTL busses.

Aeroflex UTMC lvds receiver

Contextual Info: Standard Products UT54LVDS218 Deserializer Data Sheet September 24, 2003 INTRODUCTION FEATURES The UT54LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a

dvi to lvds

Abstract: PCM-261 lvds to dvi PCM-261L-B0A1E 18-BIT silicon image 164 lcd lvds cable 24-BIT
Contextual Info: PCM-261 LVDS/TTL to DVI Module Features • Supports 18 and 24-bit LVDS to DVI • Supports 18 or 24-bit TTL LCD to DVI optional Specifications General Chipset Silicon Image SiI 164; NS DS90CF364 LCD Connector Hirose Output Connector; DVI Mechanical and Environmental

Contextual Info: SN65EPT21 www.ti.com SLLS970 – NOVEMBER 2009 3.3-V Differential PECL/LVDS to TTL Translator Check for Samples: SN65EPT21 FEATURES 1 • • • • • • 1 ns Propagation Delay Fmax > 300MHz Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V 24-mA TTL Output

Contextual Info: SN65EPT21 www.ti.com SLLS970 – NOVEMBER 2009 3.3-V Differential PECL/LVDS to TTL Translator Check for Samples: SN65EPT21 FEATURES 1 • • • • • • 1 ns Propagation Delay Fmax > 300MHz Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V 24-mA TTL Output

Contextual Info: SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396A– SEPTEMBER 1999 – REVISED NOVEMBER 1999 D D D D D D D D D Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL

Contextual Info: SN65EPT21 www.ti.com SLLS970 – NOVEMBER 2009 3.3-V Differential PECL/LVDS to TTL Translator Check for Samples: SN65EPT21 FEATURES 1 • • • • • • 1 ns Propagation Delay Fmax > 300MHz Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V 24-mA TTL Output

ECL82

Abstract: LVDS104 LVDS105 SN65LVDS104 SN65LVDS105 SN65LVDS108 SN65LVDS109 SN65LVDS116 SN65LVDS22
Contextual Info: SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 D D D D D D D D D Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL

MC10EPT21

Contextual Info: SN65EPT21 www.ti.com SLLS970 – NOVEMBER 2009 3.3-V Differential PECL/LVDS to TTL Translator Check for Samples: SN65EPT21 FEATURES 1 • • • • • • 1 ns Propagation Delay Fmax > 300MHz Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V 24-mA TTL Output

MC100EPT21

Abstract: SN65EPT21 SN65EPT21D SN65EPT21DGK
Contextual Info: SN65EPT21 www.ti.com SLLS970 – NOVEMBER 2009 3.3-V Differential PECL/LVDS to TTL Translator Check for Samples: SN65EPT21 FEATURES 1 • • • • • • 1 ns Propagation Delay Fmax > 300MHz Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V 24-mA TTL Output

LVDS105

Contextual Info: SN65LVDS104, SN65LVDS105 4ĆPORT LVDS AND 4ĆPORT TTLĆTOĆLVDS REPEATERS SLLS396E− SEPTEMBER 1999 − REVISED NOVEMBER 2004 D Receiver and Drivers Meet or Exceed the D D D D D D D D D Requirements of ANSI EIA/TIA-644 Standard − SN65LVDS105 Receives Low-Voltage TTL

LVDS104

Abstract: LVDS105 SN65LVDS104 SN65LVDS105 SN65LVDS108 SN65LVDS109 SN65LVDS116 SN65LVDS22 SN65LVDS 560AB
Contextual Info: SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396C– SEPTEMBER 1999 – REVISED AUGUST 2000 D D D D D D D D D D Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL

LVDS105

Abstract: LVDS104 SN65LVDS104 SN65LVDS105 SN65LVDS108 SN65LVDS109 SN65LVDS116 SN65LVDS22
Contextual Info: SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396D– SEPTEMBER 1999 – REVISED MAY 2001 D D D D D D D D D D Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL

Contextual Info: STLVDS105 4-PORT LVDS AND 4-PORT TTL-TO LVDS REPEATERS • ■ ■ ■ ■ ■ ■ ■ RECEIVER AND DRIVERS MEET OR EXCEED THE REQUIREMENTS OF ANSI EIA/TIA-644 STANDARD: RECEIVERS LOW-VOLTAGE TTL LVTTL LEVELS DESIGNED FOR SIGNALING RATES UP TO 630Mbps OPERATES FROM A SINGLE 3.3V SUPPLY

Contextual Info: Standard Products UT54LVDS218 Deserializer Data Sheet September, 2006 FEATURES INTRODUCTION ‰ ‰ ‰ ‰ ‰ ‰ ‰ ‰ ‰ ‰ ‰ ‰ The UT54LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a

LVDS218

Contextual Info: Standard Products UT54LVDS218 Deserializer Data Sheet September 2002 FEATURES INTRODUCTION q q q q q q q q q q q q The UT54LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 50MHz, 21 bits of TTL data are transmitted at a

Contextual Info: Standard Products UT54LVDS218 Deserializer Data Sheet December, 2008 FEATURES INTRODUCTION ‰ ‰ ‰ ‰ ‰ ‰ ‰ ‰ ‰ ‰ ‰ ‰ The UT54LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a