TTL LOGIC DATA BOOK Search Results

MC10129

Abstract: MC10129FN MC10129L MC10129P T714
Contextual Info: MC10129 Quad Bus Receiver The MC10129 data inputs are compatible with, and accept TTL logic levels as well as levels compatible with IBM–type buses. The clock, strobe, and reset inputs accept MECL 10,000 logic levels. The data inputs accept the bus levels, and storage elements are

MC10H124

Abstract: DL122 MC10H115 MC10H116
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad TTL-to-MECL Translator With TTL Strobe Input MC10H124 The MC10H124 is a quad translator for interfacing data and control signals between a saturated logic section and the MECL section of digital systems. The 10H part is a functional/pinout duplication of the standard

10H124

Abstract: MC10H115 MC10H116 MC10H124 MC10H124FN MC10H124L MC10H124P
Contextual Info: MC10H124 Quad TTL-to-MECL Translator With TTL Strobe Input The MC10H124 is a quad translator for interfacing data and control signals between a saturated logic section and the MECL section of digital systems. The 10H part is a functional/pinout duplication of the

MC10124 application

Abstract: MC10124 MC10124P MC10115 MC10116 MC10124FN MC10124L
Contextual Info: MC10124 Quad TTL to MECL Translator The MC10124 is a quad translator for interfacing data and control signals between a saturated logic section and the MECL section of digital systems. The MC10124 has TTL compatible inputs, and MECL complementary open–emitter outputs that allow use as an

Contextual Info: SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA High-Impedance State During Power Up

FB2031

Abstract: SN74FB2031 SN74FB2031RC
Contextual Info: SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA High-Impedance State During Power Up

Contextual Info: SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA High-Impedance State During Power Up

DS14C88N

Abstract: DS1488 DS14C88 DS14C88M MC1488 N14A
Contextual Info: General Description The DS14C88, pin-for-pin compatible to the DS1488/ MC1488, is a quad line drivers designed to interface data terminal equipment DTE with data circuit-terminating equipment (DCE). This device translates standard TTL/ CMOS logic levels to levels conforming to EIA-232-D and

DS14C89AN

Abstract: DS1489A DS14C89A DS14C89AM M14A MC1489A
Contextual Info: General Description The DS14C89A, pin-for-pin compatible to the DS1489A/ MC1489A, ia a quad receiver designed to interface data terminal equipment DTE with data circuit-terminating equipment (DCE). These devices translate levels conforming to EIA-232E and CCITT V.28 standards to TTL/CMOS logic

TIL306 Application Notes

Abstract: TIL306 TL306 TIL307 Seven-Segment Numeric LED Display with latch TTL 1N3064 D1034 TIL307 equivalent TIL306 equivalent BCD counter
Contextual Info: TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 – D1034, JUNE 1982 – REVISED SEPTEMBER 1992 SOLID-STATE DISPLAYS WITH INTEGRAL TTL MSI CIRCUIT CHIP FOR USE IN ALL SYSTEMS WHERE THE DATA TO BE DISPLAYED IS THE PULSE COUNT • • • • • • •

Contextual Info: Lattice GAL20V8Z Zero Power E2CMOS PLD Generic Array Logic FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15 ns Maximum Propagation Delay — Fmax =62.5 MHz — 10 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Output Drive — UltraMOS® Advanced CMOS Technology

totempole driver

Abstract: GAL16V8 GAL16VP8 GAL16VP8B-15LJ GAL16VP8B-15LP GAL16VP8B-25LJ GAL16VP8B-25LP 64-USER
Contextual Info: Specifications GAL16VP8 GAL16VP8 High-Speed E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES ® • HIGH DRIVE E CMOS GAL DEVICE — TTL Compatible 64 mA Output Drive — 15 ns Maximum Propagation Delay — Fmax = 80 MHz — 10 ns Maximum from Clock Input to Data Output

F381

Abstract: F382 MC74F381 MC74FXXXDW 74F381
Contextual Info: For:char Printed on:Mon, Feb 6, 1995 09:49:45 From book:DL121CH4 5 VIEW Document:MC74F381 (5) VIEW Last saved on:Fri, Feb 3, 1995 16:06:52 MC54/74F381 4-BIT ARITHMETIC LOGIC UNIT The MC54/74F381 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select input codes force the Function

LT 543 7-segment display datasheet

Abstract: sn74124 4046 application note pll truth table of 4017 application note pll 4046 sn 74 als 324 LT 542 seven segment display data sheet 12a h3 sc sf PLL CD 4046 logic diagram of 4bit binary ripple up counter
Contextual Info: Digital Logic Pocket Data Book Pocket Data Book Digital Logic 2003 Printed in Japan 0103 SCYD013 2003 SLL Digital Logic Pocket Data Book 名称未設定-2 1 2003.1.14, 4:12 PM IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

msi 7267 MOTHERBOARD SERVICE MANUAL

Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
Contextual Info: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

MC74F299

Abstract: MC74FXXXDW
Contextual Info: For:laurie Printed on:Sat, Aug 13, 1994 11:15:02 From book:mc54f Document:mc74f299rev5 Last saved on:Fri, Aug 12, 1994 13:38:16 MC74F299 8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER WITH COMMON PARALLEL I/O PINS 8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER WITH COMMON

2sc 9015

Abstract: L313F Johanson "RF multiplexer"
Contextual Info: OPA678 B U R R - BROWNS [ 1 AVAILABLE IN DIE Wideband Switched-lnput OPERATIONAL AMPLIFIER FEATURES APPLICATIONS • FAST SETTLING: 11ns 1% • VIDEO AMPLIFICATION AND SWITCHING • WIDE BANDWIDTH: 200MHz • FAST 2-INPUT MULTIPLEXER • TWO LOGIC SELECTABLE INPUTS

TTL LS 7400

Abstract: ttl 7400 marking WV1 transistor TTL 7400 national semiconductor 74H Logic Family Specifications IC 7400 nand gate MIL-STD-806B LS TTL family characteristics transistor f259 internal structure 74LS00 nand gate
Contextual Info: Introduction National Semiconductor Introduction FAST, an acronymn for Fairchild Advanced Schottky TTL, is a high-speed, low-power logic family that achieves speeds typically 30% faster than the Schottky family with a corre­ sponding power reduction of approximately 75%. It is fabri­

Contextual Info: SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion

Contextual Info: SN10KHT5574 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS SDZS010 – JANUARY 1990 – REVISED OCTOBER 1990 • • • • • DW OR NT PACKAGE TOP VIEW 10KH Compatible ECL Clock and TTL Control Inputs 1Q 2Q 3Q 4Q

sn74ls151 multiplexer vhdl code

Abstract: MC14500B MC667 MC14000B MC672 equivalent MC661 MC672 MC660 bounce eliminator mc12073
Contextual Info: Logic: Standard, Special and Programmable In Brief . . . Page Motorola Programmable Arrays MPA . . . . . . . . . . . . 3.1–1 Selection by Function Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–8 Device Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–36

AN-514

Abstract: DM74AS373 DM74AS374
Contextual Info: ABSTRACT This paper presents detailed examples of bus timing calculations for both synchronous and asynchronous busses, showing that bus throughput can be maximized by taking into account the characteristics and limitations of the transceiver technology being used. Based on these examples, a performance analysis of the currently available high speed bus interface technologies is made in terms of their maximum attainable transfer rate on both types of backplane busses.

SN10KHT5573

Contextual Info: SN10KHT5573 OCTAL ECLĆTOĆTTL TRANSLATOR WITH DĆTYPE TRANSPARENT LATCHES AND 3ĆSTATE OUTPUTS SDZS015 − MAY 1990 − REVISED OCTOBER 1990 • • • • • • DW OR NT PACKAGE T0P VIEW 10KH Compatible ECL and TTL Control Inputs 1Q 2Q 3Q 4Q VCC GND

Contextual Info: a P R E L IM IN A R Y Advanced Micro Devices Am79865/Am79866A Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS • Parallel Input to the PDT is a 5-blt encoded NRZ symbol clocked by LSCLK 125 MBaud 100 Mbps serial link data rate