TTL LOGIC Search Results

740L6000

Abstract: transistor c2026 c2026 c2026 transistor data 740L6010 transistor equivalent c2026 740L6011 C2026 TRANSISTOR 740L6001 c2037
Contextual Info: HIGH-SPEED LOGIC-TO’LOGIC OPTOCOUPLERS OPTOELECTRONICS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTLto ORDER INFORMATION LOGIC COMPATIBILITY PART NUMBER INPUT OUTPUT TTL 740L6000 LSTTL TTL 740L6001 LSTTL CMOS 740L6010 LSTTL CMOS 740L6011 LSTTL

Contextual Info: IDT74GTLP816 GTLP / TTL 1:2 / 1:6 CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE GTLP/TTL 1:2/1:6 CLOCK DRIVER FEATURES: • • • • • • • • DESCRIPTION: 5V or 3.3V operation Interface between GTLP and TTL logic levels GTLP to TTL 1:6 fanout TTL to GTLP 1:2 fanout

Contextual Info: IDT74GTLP816 GTLP / TTL 1:2 / 1:6 CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE GTLP/TTL 1:2/1:6 CLOCK DRIVER FEATURES: • • • • • • • • DESCRIPTION: 5V or 3.3V operation Interface between GTLP and TTL logic levels GTLP to TTL 1:6 fanout TTL to GTLP 1:2 fanout

IDT74GTLP816

Contextual Info: IDT74GTLP816 GTLP / TTL 1:2 / 1:6 CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE GTLP/TTL 1:2/1:6 CLOCK DRIVER FEATURES: • • • • • • • DESCRIPTION: Interface between GTLP and TTL logic levels GTLP to TTL 1:6 fanout TTL to GTLP 1:2 fanout Edge Rate Control Circuit reduces output noise on GTLP port

MSI Logic

Abstract: UT54ACS14E ut54acts541e UT54ACTS02E UT54ACS14 Tri-State Buffer CMOS cmos msi data book cmos TTL LOGIC DATA BOOK UT54ACS373
Contextual Info: Aeroflex MSI Logic IBIS model Buffer Identification 4/16/2009 Tri-State Devices Input Buffer CMOS TTL Output Buffer 8mA 8mA UT54ACS273 UT54ACTS04 CMOS CMOS E TTL TTL (E) 8mA 8mA 8mA 8mA UT54ACS273 UT54ACS02E UT54ACTS04 UT54ACTS08E CMOS TTL 8mA 8mA UT54ACS273

IC TTL 74LS00

Abstract: TTL LS 7400 IC TTL 74 ls 04 7400 fan-out cmos 7400 fan-out TTL 7400 catalog TTL 74ls00 TTL 7400 rise and fall time of ic 74ls00 74LS00 gate
Contextual Info: Design Considerations, Testing and Applications Assistance Form FAST AND LS TTL FAST AND LS TTL DATA 3-1 3 DESIGN CONSIDERATIONS SELECTING TTL LOGIC. TTL Families may be mixed in a system for optimum performance. For instance, in new designs, ALS would commonly be used in non-critical speed paths to minimize power consumption while FAST TTL would be used in high

CY101E383

Abstract: E383 R2170 ecl 84
Contextual Info: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-

Contextual Info: O SYNERGY SEMICONDUCTOR 3.3V SINGLE SUPPLY OCTAL PECL/TTL-TO-TTL PECL/TTL-to-TTL version of popular ECLinPS E111AE/LE Guaranteed low skew specification Three-state enable Differential internal design V bb output for single-ended operation Extra TTL and ECL power/ground pins

ttlpd

Abstract: 125OC TTLPD-10 TTLPD-10M TTLPD-15 TTLPD-15M TTLPD-20 TTLPD-25 TTLPD-30
Contextual Info: TTLPD Series FAST / TTL Pulse Width Discriminator Modules Electrical Specifications at 25OC FAST / TTL Pulse Width Discriminator Modules 14-Pin Package Commercial and Mil-Grade Versions FAST/TTL Logic Buffered Pass Pulse Widths above & suppress Pulses below Nominal Value

HLT28

Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

HLT28

Abstract: KLT28 MC100 MC100ELT28 MC10ELT28 transistor k 4110
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

Contextual Info: ^ LOW POWER HEX TTL-tO-ECL TRANSLATOR SYNERGY SY100S324 SEMICONDUCTOR DESCRIPTION FEATURES The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL compatible with differential outputs that can either be used

PDU-1316-20

Abstract: PDU-1316-1 PDU-1316-12 PDU-1316-2 PDU-1316-5 PDU-1316-100 NS225
Contextual Info: data \flaa Digitally Programmable delay \ë SERIES: PDU-1316 De ay Units deviceli«:. 4-Bit TTL Interfaced Specifications: Test Conditions: • Input signal requirement: TTL logic ■ Output fan-out: TTL schottky load ■ Delay variation: Monotonic in one direction

Contextual Info: * SYNERGY LOW-POWER HEX TTL-TO-PECL TRANSLATOR SY100S391 SEMICONDUCTOR DESCRIPTION FEATURES Operates from a single +5V supply Differential PECL outputs The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique

Contextual Info: 14 PIN TTL SCHOTTKY SQUARE WAVE GENERATOR 53A SERIES FEATURES • • • • • 14-PIN PACKAGE. 10 TTL FAN-OUT CAPACITY. TTL SCHOTTKY INTERFACED. OUTPUT FREQUENCY TOLERANCE:±2%. OUTPUT DUTY CYCLE:50%±5% ELECTRICAL CHARACTERISTICS IIH Logic”1” Input Current

GTLP8T306

Abstract: MTC24
Contextual Info: March 1998 GTLP8T306 8-Bit TTL-to-GTLP Bus Transceivers Preliminary General Description Features The GTLP8T306 is an 8-bit bus transceiver that provides TTL to GTLP signal level translation. The device provides a high speed interface between cards operating at TTL logic

100324

Contextual Info: Revised November 1999 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable

Contextual Info: IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER FEATURES: • • • • • DESCRIPTION: Bidirectional interface between GTLP and TTL logic levels Edge Rate Control Circuit reduces output noise

GTLP16612

Abstract: IDT74GTLP16612
Contextual Info: IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER FEATURES: • • • • • DESCRIPTION: Bidirectional interface between GTLP and TTL logic levels Edge Rate Control Circuit reduces output noise

100324PC

Abstract: 100324QC 100324QI 100324SC M24B MS-013 N24E V28A 100124 100324
Contextual Info: Revised August 2000 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable

Contextual Info: * LOW-POWER HEX TTL-TO-PECL TRANSLATOR SYNERGY SY100S391 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this

AI3D-12

Abstract: AI3D-15 AI3D-20 AI3D-25 AI3D-30 AI3D-35 AI3D-10 AI3D-11
Contextual Info: AI3D Series FAST / TTL Buffered Triple Independent Delays Electrical Specifications at 25OC 14-Pin Package Surface Mount and Thru-hole Versions Delay Tolerance ns FAST/TTL Logic Buffered 14-Pin 74F/TTL Buffered Triple Independent Delays DIP P/N G-SMD P/N

A1610

Abstract: 100324
Contextual Info: Revised March 2001 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable

ttlpwg

Abstract: 125OC TTLPWG-10 TTLPWG-15 TTLPWG-20 TTLPWG-25 TTLPWG-30 TTLPWG-35 "FAST TTL"
Contextual Info: TTLPWG Series FAST / TTL Pulse Width Generator Modules Electrical Specifications at 25OC 14-Pin Package Commercial and Mil-Grade Versions FAST / TTL Buffered Pulse Width Generator Modules FAST/TTL Logic Buffered Part Number Precise Pulse Width Output triggered by Rising Edge of Input