TTL BUFFER SIGNAL Search Results

74LS04 fan-out

Abstract: 74OL6011 6010 OPTOCOUPLER
Contextual Info: OPTOPLANAR HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO PACKAGE 6 74OL6000 74OL6001 74OL6010 74OL6011 SYMBOL BUFFER 6 1 1 INVERTER 6 1 DESCRIPTION OPTOLOGIC is the first family of truly logic compatible optically coupled logic interface gates.

Contextual Info: SN65ELT23 www.ti.com. SLLS925 – JUNE 2009 5-V Dual Differential PECL Buffer-to-TTL Translator

MC100ELT23

Abstract: SN65ELT23 SN65ELT23D SN65ELT23DGK SN65ELT23DGKR SN65ELT23DR
Contextual Info: SN65ELT23 www.ti.com. SLLS925 – JUNE 2009 5-V Dual Differential PECL Buffer-to-TTL Translator

Contextual Info: GA11 1 0 M ulti-Phase Clock G enerator Low -Skew TTL Clock Buffer r gazelle Features G eneral Description Gazelle’s GA1110 is a low-skew TTL-level clock buffer chip with : multi-phase clock generation. It produces multiple clock outputs which are phase and frequency synchronized to a periodic clock

Contextual Info: Ô Q u a l it y S e m ic o n d u c t o r , I n c . Guaranteed Low Skew CMOS Clock Driver/Buffer QS5807T QS52807T FEATURES/BENEFITS DESCRIPTION • 10 output, low skew clock signal buffer • TTL output voltage swing • 25Q on-chip resistors available for low noise

Contextual Info: bel/defining a degree of excellence DIGITAL DELAY LINE SERIES 0449 TTLPROGRAMMABLE LOGIC DELAY MODULE 3 BIT TECHNICAL INFORMATION TEST CONDITIONS Driving Signal Schottky TTL Buffer Pulse Width 1.5 x Maximum Delay 5 x Pulse Width Pulse Period 50.0 Milliamps

HCT244A

Abstract: TC74HCT240 TC74HCT240AF TC74HCT240AP TC74HCT244AF TC74HCT244AP
Contextual Info: TC74HCT240,244AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT240AP,TC74HCT240AF TC74HCT244AP,TC74HCT244AF Octal Bus Buffer with TTL Input Level TC74HCT240AP/AF Inverted, 3-State Outputs TC74HCT244AP/AF Non-Inverted, 3-State Outputs

Contextual Info: TC74HCT540,541AP/AF/AFW TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT540AP,TC74HCT540AF,TC74HCT540AFW TC74HCT541AP,TC74HCT541AF,TC74HCT541AFW Octal Bus Buffer with TTL Input Level TC74HCT540AP/AF/AFW Inverting, 3-State Outputs TC74HCT541AP/AF/AFW Non-Inverting,

Contextual Info: Guaranteed Low Skew PECL-TTL Clock Driver/Buffer Q u a l it y S e m ic o n d u c t o r , I n c . QS5P807T QS5P2807T FEATURES/BENEFITS DESCRIPTION • PECL clock input • 10 TTL clock output, • 25Q on-chip resistors available for low noise • Guaranteed low skew

R301D

Contextual Info: 74ACT11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS145- D3435, MARCH 199Q-REVISEDAPRIL1993 DW OR N PACKAGE * Inputs Are TTL-Voltage Compatible TOP VIEW * Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators * Fully-Buffered Outputs for Maximum

Contextual Info: Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 LMK00804B Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer 1 Features • 1 • • •

TC7SET125F

Abstract: TC7SET125FU
Contextual Info: TC7SET125F/FU TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7SET125F,TC7SET125FU Bus Buffer Features • TC7SET125F High speed : tpd = 3.7 ns typ. at VCC = 5 V, CL = 15pF • Low power dissipation • Compatible with TTL outputs. : VIL = 0.8 V (max)

TC7SET126F

Abstract: TC7SET126FU
Contextual Info: TC7SET126F/FU TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7SET126F,TC7SET126FU Bus Buffer Features • TC7SET126F High speed : tpd = 3.7 ns typ. at VCC = 5 V, CL = 15pF • Low power dissipation • Compatible with TTL outputs. : VIL = 0.8 V (max)

LM106

Abstract: LM306 LM106H LM306H LM710 DS007756 LM106H/883C
Contextual Info: General Description The LM106 series are high-speed voltage comparators designed to accurately detect low-level analog signals and drive a digital load. They are equivalent to an LM710, combined with a two input NAND gate and an output buffer. The circuits can drive RTL, DTL or TTL integrated circuits directly.

74AUP1G240GW

Abstract: MO-203 74AUP1G240 74AUP1G240GF 74AUP1G240GM
Contextual Info: 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 01 — 6 November 2006 Product data sheet 1. General description The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Contextual Info: >kiyixi>ki CMOS Quad 8 -B it D /A C onverters _ Features Maxim's AD7225 and AD7226 each contain four 8-bit voltage output digital-to-analog converters DACs . They include output buffer amplifiers and input logic for simple microprocessor and TTL/CMOS interfaces.

d172d

Abstract: CAS08
Contextual Info: 74ACT11175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR _ SCASQ89 - D3385. D E CEM BER 1989 - R E V IS E D APRIL 1933 * Inputs Are TTL-Voltage Compatible * Buffered Clock and Direct Clear Inputs * Applications Include: Buffer/Storage Registers, Shift Registers, Pattern

Contextual Info: 74ACT11273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SCAS130- D3443, MARCH 1990-R EV ISË D APRIL1993 DW OR NT PACKAGE TOP VIEW * Inputs Are TTL-Voltage Compatible * Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators * Flow-Through Architecture Optimizes

Contextual Info: Integrated Circuit Systems,Inc. ICS9176 Advance Information Low Skew Output Buffer Features • ICS9176-01 is pin compatible with Triquint GA1086 • ±500 ps skew max between input and outputs • +250 ps skew (max) between outputs • 10 symmetric, TTL-compatible outputs

Contextual Info: I N I Q U I C O M P U T I N G AND -V ' S E M I C 0 N D U T1 T O F , I N C N E T W O R K I N G GA1110E Figure 1. Block Diagram VDD C C LK IN F B IN S1 SO TO GND Data Sheets Multi-Phase Clock Buffer Features • Zero-propagation-delay clock buffer TriQuint's GA1110E is a low -skew TTL-level clock buffer chip w ith m ulti-phase clock

8614

Abstract: SEP8506 SEP8706 visible detector
Contextual Info: SDP8604/8614 Optoschmitt Detector 10 k Ohm Pull-Up Output FEATURES • Side-looking plastic package • 55¡ nominal acceptance angle • TTL/LSTTL/CMOS compatible • 10ì pull- up output • Buffer or inverting logic available • High noise immunity output

core i7 Absolute maximum rating

Contextual Info: Standard Products UT54ACTQ16244 RadHard CMOS 16-bit Buffer/Line Driver, TTL Inputs, and Three-State Outputs Advanced Datasheet October 13, 2006 www.aeroflex.com/radhard LOGIC SYMBOL OE1 ‰ 16 non-inverting buffers with three-state outputs ‰ Guaranteed simultaneously switching noise level and dynamic threshold performance

Contextual Info: 74ACT11175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCAS089 – D3385, DECEMBER 1989 – REVISED APRIL 1993 • • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Buffered Clock and Direct Clear Inputs Applications Include: Buffer/Storage

FZH115B

Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Contextual Info: Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P