TTL BUFFER SIGNAL Search Results

ttl inverter

Abstract: INVERTER TRANSFORMERS design 74LS04 fan-out 74OL6000 74OL6000-6010 UF74OL 74OL6011 pin configuration 74LS04 trace inverter schematic 74ol6000 equivalent
Contextual Info: OPTOPLANAR HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO PACKAGE 6 74OL6000 74OL6001 74OL6010 74OL6011 SYMBOL BUFFER 6 1 1 INVERTER 6 1 DESCRIPTION OPTOLOGIC is the first family of truly logic compatible optically coupled logic interface gates.

74LS04 fan-out

Abstract: 74OL6011 6010 OPTOCOUPLER
Contextual Info: OPTOPLANAR HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO PACKAGE 6 74OL6000 74OL6001 74OL6010 74OL6011 SYMBOL BUFFER 6 1 1 INVERTER 6 1 DESCRIPTION OPTOLOGIC is the first family of truly logic compatible optically coupled logic interface gates.

74LS04 fan-out

Abstract: 74LS04 fan-in 7ls04 6010 OPTOCOUPLER 74OL6011
Contextual Info: OPTOPLANAR HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO PACKAGE 6 74OL6000 74OL6001 74OL6010 74OL6011 SYMBOL BUFFER 6 1 1 INVERTER 6 1 DESCRIPTION OPTOLOGIC is the first family of truly logic compatible optically coupled logic interface gates.

ttl inverter

Abstract: 7ls04
Contextual Info: OPTOPLANAR HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO PACKAGE 6 74OL6000 74OL6001 74OL6010 74OL6011 SYMBOL BUFFER 6 1 1 INVERTER 6 1 DESCRIPTION OPTOLOGIC is the first family of truly logic compatible optically coupled logic interface gates.

ttl inverter

Abstract: 74OL6000 74OL6001 74OL6010 74OL6011
Contextual Info: HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 SYMBOL 6 1 6 BUFFER 1 PIN CONFIGURATION 6 1 1-VCCI Input VCC 6-VCCO (Output VCC) 2-VIN (Data In) 5-VO (Data Out) 3-GND, (Input GND)

74OL6000

Abstract: 74ol6000 equivalent 74OL6001 74OL6010 74OL6011 74LS04 fan-out DS-30020 Optocouplers for ttl output Inverter Gates
Contextual Info: HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 SYMBOL 6 1 6 BUFFER 1 PIN CONFIGURATION 6 1 1-VCCI Input VCC 6-VCCO (Output VCC) 2-VIN (Data In) 5-VO (Data Out) 3-GND, (Input GND)

Contextual Info: SN65ELT23 www.ti.com. SLLS925 – JUNE 2009 5-V Dual Differential PECL Buffer-to-TTL Translator

Contextual Info: SN65ELT23 www.ti.com. SLLS925 – JUNE 2009 5-V Dual Differential PECL Buffer-to-TTL Translator

MC100ELT23

Abstract: SN65ELT23 SN65ELT23D SN65ELT23DGK SN65ELT23DGKR SN65ELT23DR
Contextual Info: SN65ELT23 www.ti.com. SLLS925 – JUNE 2009 5-V Dual Differential PECL Buffer-to-TTL Translator

Contextual Info: GA11 1 0 M ulti-Phase Clock G enerator Low -Skew TTL Clock Buffer r gazelle Features G eneral Description Gazelle’s GA1110 is a low-skew TTL-level clock buffer chip with : multi-phase clock generation. It produces multiple clock outputs which are phase and frequency synchronized to a periodic clock

40-pin QVSOP

Contextual Info: QS5820T Preliminary Information Q Guaranteed Low Skew CMOS QS5820AT QS5820BT 20 Output Clock Driver/Buffer FEATURES • 20 output, low skew clock signal buffer • High drive FCT-type outputs • Reduced swing TTL outputs for low noise • Input hysteresis for better noise margin

qs52805atq

Abstract: ob3 diode
Contextual Info: ADVANCED INFORMATION QS5805T/AT, QS52805T/AT QS5806T/AT, QS52806T/AT Guaranteed Low Skew CMOS Clock Driver/Buffer FEATURES • 10 output, low skew clock signal buffer • 25 Q on-chip resistors available for low noise • Reduced swing TTL outputs for low noise

AN-21

Abstract: QS5P2807ATQ
Contextual Info: QS5P807T, QS5P2807T Guaranteed Low Skew PECL-TTL Clock Driver/Buffer Q QUALITY SEMICONDUCTOR, INC. QS5P807T QS5P2807T FEATURES/BENEFITS DESCRIPTION • • • • The QS5P807T clock driver/buffer circuits can be used for clock buffering schemes where low skew is a key

MK3807-01

Abstract: MK3807-01RI MK3807-01RILF MK3807-01RITR
Contextual Info: DATASHEET MK3807-01 BUFFER/CLOCK DRIVER Description Features The MK3807-01 is a low skew 3.3 V, 1 to 10 fanout buffer. The large fanout from a single input line reduces loading on the input clock. The TTL level outputs reduce noise levels on the part. Typical applications are clock and signal

MK3807-01

Abstract: MK3807-01RI MK3807-01RILF MK3807-01RITR
Contextual Info: DATASHEET MK3807-01 BUFFER/CLOCK DRIVER Description Features The MK3807-01 is a low skew 3.3 V, 1 to 10 fanout buffer. The large fanout from a single input line reduces loading on the input clock. The TTL level outputs reduce noise levels on the part. Typical applications are clock and signal

Contextual Info: '.fit PRELIMINARY DEVICE SPECIFICATION MULTI-PHASE CLOCK GENERATOR/LOW-SKEW TTL CLOCK BUFFER SC1110 I FEATURES GENERAL DESCRIPTION • Pin-for-pin replacement for Triquint/Gazelle GA1110E • “Zero-propagation delay” clock buffer provides ±250 ps typ , ±1 ns (max) input to output delay

Contextual Info: Ô Q u a l it y S e m ic o n d u c t o r , I n c . Guaranteed Low Skew CMOS Clock Driver/Buffer QS5807T QS52807T FEATURES/BENEFITS DESCRIPTION • 10 output, low skew clock signal buffer • TTL output voltage swing • 25Q on-chip resistors available for low noise

C2036

Abstract: transistor C2003 K C2028 Y 740L6010 740L6000 C2010 transistor 740L600 c2038 transistor c2030 c2028
Contextual Info: HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS # 4 1 im Ë iïc m ilïS A i c it i OPTOfiOGfC T« PART NUMBER 740L6000 74DL6Ö01 740L6010 740L6011 TTL BUFFER tn m INVERTER CMOS BUFFER CMOS INVERTER 740L6000 740L6001 740L6010 740L6Ö11 LOGIC COMPATIBILITY INPUT LSTTL

Contextual Info: Figure 1. Block Diagram GA1110E Multi-Phase Clock Buffer Features * T riQ uint’s GA1110E is a low -skew TTL-level clock buffer chip w ith m ulti-phase clock * generation. It produces m ultiple clock outputs w hich are n orm ally phase- and frequency- Zero-propagation-delay clock

irf 7193 c

Abstract: RS flip flop IC TGS 815 irf 44 ns XC115 94Q3 9403
Contextual Info: 9403 '/ FIRST-IN FIRST-OUT FIFO BUFFER MEMORY F A IR C H IL D TTL MACROLOGIC D E S C R IP T IO N - The 9403 is an expandable fall-through type high-speed First-In First-Out ( F IF O ) Buffer Memory optimized for high speed disc or tape controllers and com m unication buffer applications. It is organized as 16 words by four bits and may be

Contextual Info: bel/defining a degree of excellence DIGITAL DELAY LINE SERIES 0449 TTLPROGRAMMABLE LOGIC DELAY MODULE 3 BIT TECHNICAL INFORMATION TEST CONDITIONS Driving Signal Schottky TTL Buffer Pulse Width 1.5 x Maximum Delay 5 x Pulse Width Pulse Period 50.0 Milliamps

M7540

Contextual Info: Preliminary AT&T DATA SHEET 439C Sub-Band Decoder FEATURES • 64 x 8-bit input FIFO memory buffer • TTL-compatible inputs and outputs • 64 x 8-bit output FIFO memory buffer • FCC part 68.308 protection circuitry • Decodes 16 kb/s or 24 kb/s • Multichannel operation under host control

439C

Contextual Info: Prelim inary AT&T DATA SHEET 439C S u b-B a nd D ecoder FEATURES • 64 x 8-bit input FIFO memory buffer • TTL-compatible inputs and outputs • 64 x 8-bit output FIFO memory buffer • FCC part 68.308 protection circuitry • Decodes 16 kb/s or 24 kb/s

74LS540

Abstract: TC74HCT540 TC74HCT540AF TC74HCT540AP TC74HCT541AF TC74HCT541AP
Contextual Info: TC74HCT540,541AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT540AP,TC74HCT540AF TC74HCT541AP,TC74HCT541AF Octal Bus Buffer with TTL Input Level TC74HCT540AP/AF Inverting, 3-State Outputs TC74HCT541AP/AF Non-Inverting, 3-State Outputs