TTL AND GATE Search Results

KLT28

Abstract: HLT28 HT28 KT28 MC100ELT28 MC10ELT28 transistor k 4110
Contextual Info: MC10ELT28, MC100ELT28 5V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are

HLT28

Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

DM74ALS

Abstract: DM74ALS02 DM74ALS02M DM74ALS02N DM74ALS02SJ M14A M14D N14A
Contextual Info: National Semiconductor DM74ALS02 Quad 2-Input NOR Gate Advanced oxide-isolated, ion-implanted Schottky TTL process Functionatly and pin for pin compatible with Schottky and low power Schottky TTL counterpart Improved AC performance over Schottky and low pow­

DM74ALS00N

Abstract: DM74ALS 74ALS DM74ALS00A M14A N14A MUD 112
Contextual Info: OOA & National Semiconductor DM74ALS00A Quad 2-Input NAND Gate Advanced oxide-isolated, ion-implanted Schottky TTL process Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart Improved AC performance over Schottky and low pow­

74ALS

Abstract: DM74ALS DM74ALS11A DM74ALS11AM DM74ALS11AN M14A N14A
Contextual Info: General Description This device contains three independent gates, each of which performs the logic AND function. Features n Advanced oxide-isolated, ion-implanted Schottky TTL process n Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart

M14A

Abstract: N14A 74ALS DM74ALS DM74ALS21A DM74ALS21AM DM74ALS21AN
Contextual Info: General Description This device contains two independent gates, each of which performs the logic AND function. Features n Advanced oxide-isolated, ion-implanted Schottky TTL process n Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart

DM74ALS27

Abstract: 74ALS DM74ALS DM74ALS27M DM74ALS27N M14A N14A
Contextual Info: DM74ALS27 Triple 3-Input NOR Gate n Advanced oxide-isolated, ion-implanted Schottky TTL process n Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart n Improved AC performance over Schottky and low power Schottky counterparts

KK74HCT21A

Abstract: KK74HCT21AD KK74HCT21AN
Contextual Info: TECHNICAL DATA KK74HCT21A Dual 4-Input AND Gate The KK74HCT21A is high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL LSTTL . The device provide the Dual 4-input AND function. • Outputs Directly Interface to CMOS, NMOS, and TTL

DP8481

Contextual Info: DP8481 DP8481 TTL to 10k ECL Level Translator with Latch Literature Number: SNOSBN9A DP8481 TTL to 10k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

Contextual Info: DP8483 DP8483 TTL to 100k ECL Level Translator with Latch Literature Number: SNOSBO1A DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

Contextual Info: National Semiconductor DM74AS08 Quad 2-Input AND Gate • Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Functionally and pin for pin compatible with Schottky, low power Schottky, and advanced low power Schottky TTL counterpart ■ Improved AC performance over Schottky, low power

intel 3207

Abstract: DS75365N C1995 DS75365 DS75365WM M16B N16A vc2f A24V-4
Contextual Info: DS75365 Quad TTL-to-MOS Driver Y General Description Y The DS75365 is a quad monolithic integrated TTL-to-MOS driver and interface circuit that accepts standard TTL input signals and provides high-current and high-voltage output levels suitable for driving MOS circuits It is used to drive

KK74HC21A

Abstract: KK74HC21AD KK74HC21AN
Contextual Info: TECHNICAL DATA KK74HC21A Dual 4-Input AND Gate The KK74HC21A is high-speed Si-gate CMOS device and is pin compatible with pullup resistors with low power Schottky TTL LSTTL . The device provide the Dual 4-input AND function. • Outputs Directly Interface to CMOS, NMOS, and TTL

DM74ALS

Abstract: DM74ALS20A DM74ALS20AM DM74ALS20AN M14A N14A
Contextual Info: General Description This device contains two independent gates, each of which performs the logic NAND function. Features n Advanced oxide-isolated, ion-implanted Schottky TTL process n Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs MC74HCT273A * High-Performance Silicon-Gate CMOS 1 • • TTL/NM OS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL •

DM74ALS

Abstract: DM74ALS04B DM74ALS04BM DM74ALS04BN DM74ALS04BSJ M14A M14D N14A
Contextual Info: General Description This device contains six independent gates, each of which performs the logic INVERT function. Features n Advanced oxide-isolated, ion-implanted Schottky TTL process n Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart

7547

Abstract: 74ALS DM74ALS DM74ALS27 DM74ALS27M DM74ALS27N M14A N14A
Contextual Info: n Advanced oxide-isolated, ion-implanted Schottky TTL process n Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart n Improved AC performance over Schottky and low power Schottky counterparts General Description This device contains three independent gates, each of which

KLT20

Abstract: HLT20 SO-8 HLT20 TSSOP-8 socket ic so8 socket
Contextual Info: MC10ELT20, MC100ELT20 5V TTL to Differential PECL Translator The MC10ELT/100ELT20 is a TTL to differential PECL translator. Because PECL Positive ECL levels are used, only +5 V and ground are required. The small outline 8-lead package and the single gate of

DM74ALS

Abstract: DM74ALS86 DM74ALS86M DM74ALS86N M14A N14A
Contextual Info: General Description This device contains four independent gates, each of which performs the logic exclusive-OR function. Features n Advanced oxide-isolated, ion-implanted Schottky TTL process n Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart

KLT21

Abstract: HLT21 ELT21 HT21 MC100ELT21 MC10ELT21 MC10ELT21DR2
Contextual Info: MC10ELT21, MC100ELT21 5V Differential PECL to TTL Translator The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL Positive ECL levels are used, only +5 V and ground are required. The small outline 8-lead package and the single gate of

74LS14 not gate

Abstract: 74LS14 ttl 74ls14 74ls13 74ls14 ttl equivalent for 74LS13 TTL Schmitt-Trigger Inverters TTL Schmitt-Trigger LOW POWER SCHOTTKY 74 LS 14 Logic Gates 74LS14 datasheet
Contextual Info: SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS/ 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into

KLT25

Abstract: HLT25 mst 720 ELT25 MC100ELT25 MC10ELT25
Contextual Info: MC10ELT25, MC100ELT25 Differential ECL to TTL Translator The MC10ELT/100ELT25 is a differential ECL to TTL translator. Because ECL levels are used a +5V, -5.2V or -4.5V and ground are required. The small outline 8-lead SOIC package and the single gate of

KK74HC27A

Abstract: KK74HC27AD KK74HC27AN
Contextual Info: TECHNICAL DATA KK74HC27A Triple 3-Input NOR Gate The KK74HC27A is high-speed Si-gate CMOS device and are pin compatible with low power Schottky TTL LSTTL . The device provide Triple 3-input NOR function. • Outputs Directly Interface to CMOS, NMOS, and TTL

AZ100ELT22

Abstract: ARIZONA MICROTEK
Contextual Info: AZ100ELT22 Dual CMOS/TTL to Differential PECL Translator DESCRIPTION The AZ100ELT22 is a dual CMOS/TTL to differential PECL translator. Because PECL Positive ECL levels are used, only VCC and ground are required. The small outline packaging and the low skew, dual gate design of