TTL 3 INPUT OR GATE Search Results

SL74HCT10

Abstract: SL74HCT10D SL74HCT10N
Contextual Info: SL74HCT10 Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS The SL74HCT10 is identical in pinout to the LS/ALS10. The SL74HCT10 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels

nmos to ttl interface

Abstract: ALS10 IN74HCT10D
Contextual Info: TECHNICAL DATA IN74HCT10 Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS The IN74HCT10 is identical in pinout to the LS/ALS10. The IN74HCT10 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels

KK74HCT10AN

Abstract: KK74HCT10A KK74HCT10AD
Contextual Info: TECHNICAL DATA KK74HCT10A Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS The KK74HCT10A is identical in pinout to the LS/ALS10. The KK74HCT10A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels

KK74ACT10

Abstract: KK74ACT10D KK74ACT10N
Contextual Info: TECHNICAL DATA KK74ACT10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The KK74ACT10 is identical in pinout to the LS/ALS10, HC/HCT10. The KK74ACT10 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels

IN74ACT27D

Abstract: IN74ACT27N
Contextual Info: TECHNICAL DATA IN74ACT27 Triple 3-Input NOR Gate High-Speed Silicon-Gate CMOS The IN74ACT27 is identical in pinout to the LS/ALS27, HC/HCT27. The IN74ACT27 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels

IN74ACT10D

Abstract: IN74ACT10N 5540a
Contextual Info: TECHNICAL DATA IN74ACT10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The IN74ACT10 is identical in pinout to the LS/ALS10, HC/HCT10. The IN74ACT10 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels

5540A

Abstract: IN74ACT27D IN74ACT27N
Contextual Info: TECHNICAL DATA IN74ACT27 Triple 3-Input NOR Gate High-Speed Silicon-Gate CMOS The IN74ACT27 is identical in pinout to the LS/ALS27, HC/HCT27. The IN74ACT27 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels

1016E

Abstract: 1032E 0163B ispLSI1000
Contextual Info: 1000 and 1000E Family Architectural Description input, registered input, latched input, output or bidirectional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output

KK74ACT27

Abstract: KK74ACT27D KK74ACT27N
Contextual Info: TECHNICAL DATA KK74ACT27 Triple 3-Input NOR Gate High-Speed Silicon-Gate CMOS The KK74ACT27 is identical in pinout to the LS/ALS27, HC/HCT27. The KK74ACT27 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels

"XOR Gate"

Abstract: 1032E 1016E 1048E 1000EA 0163B ispLSI1000
Contextual Info: 1000EA, 1000E and 1000 Family Architectural Description input, registered input, latched input, output or bidirectional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output

ispLSI1000

Abstract: 1016E 1032E
Contextual Info: 1000 and 1000E Family Architectural Description input, registered input, latched input, output or bidirectional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output

751A-02

Abstract: H12Y 74f51
Contextual Info: MC54/74F51 DUAL 2-WIDE 2-INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATE CONNECTION DIAGRAM VCC 1C 1B 1F 1E 1D 1Y 14 13 12 11 10 9 8 DUAL 2-WIDE 2-INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATE FAST SCHOTTKY TTL 1 2 3 4 5 6 7 1A 2A 2B 2C 2D 2Y GND J SUFFIX CERAMIC CASE 632-08

74ACT11086

Contextual Info: i TEXAS INSTR LOGIC 31E D M DDfia534 3 • T I I 3 54ACT11086, 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES ' T ' ({3 'Z -l~ o O TO 185— D3380, NOVEMBER 1989 Inputs are TTL-Voltage Compatible 54ACT11086 . . . J PACKAGE 74ACT11086 . . . D OR N PACKAGE

ORP 12

Abstract: ispLSI1000
Contextual Info: Lattice " ! Corporation 1000 and 1000E Family Architectural Description input, registered input, latched input, output or bidirec­ tional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output

74128

Abstract: TTL 74125 DM54126 DM70 DM7093 DM7094 DM8093 DM8094 y102-A2 W8-094
Contextual Info: M Additional Devices D M 70/DM 8093, 94 TRI-STATE Quad Buffers General Description The D M 7 0 9 3 /0 M 8 0 9 3 and D M 7094/D M 8094 are quad two-input buffers which accept normal TTL or OTL input lev­ el«; and have outputs which provide either normal k>wim pedance TTL characteristics, or a high-impedance third

Contextual Info: I LS TTL DN74LS Series DN74LS51 DN74LS51 2-w id e 3-input, 2-w id e 2-input AND-OR-INVERT Gates • Description P-1 DN74LS51 contains two 2-input and two 3-input AND-ORINVERT gates. ■ Features • Low power consumption P j = 5.5mW typical • High speed (tp<j = 12ns typical)

5v constant power supply lob

Abstract: D107 DN74LS32
Contextual Info: LS TTL DN74LS Series DN74LS32 D N 74L S 32 î 3^ Quad 2 - input Positive OR Gates • D escription DN74LS32 contains four 2-input positive isolation OR gate circuits. P-1 H Features • • • • Low power consumption Pd = 20mW typical) High speed (tpd = 14ns typical)

751A-02

Abstract: 74f64 motorola
Contextual Info: MC54/74F64 4-2-3-2-INPUT AND-OR-INVERT GATE 4-2-3-2-INPUT AND-OR-INVERT GATE FAST SCHOTTKY TTL VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 14 7 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

TFK U 111 B

Abstract: D3S94 74ACT11802
Contextual Info: 74ACT11802 TRIPLE 4-INPUT OR/NOR GATE S CAS153A - D3594, JULY 1990 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible DW OR NT PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout 1 2 3 4 5 6 7 8 9 10 3 Z [ 11 3 D [ 12 1a [ 1y [ 1Z [ 2Y[ gnd[

SN54ACT11

Abstract: SN74ACT11
Contextual Info: SN54ACT11, SN74ACT11 TRIPLE 3-INPUT POSITIVE-AND GATES SCAS531A – AUGUST 1995 – REVISED APRIL 1996 D D D SN54ACT11 . . . J OR W PACKAGE SN74ACT11 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54ACT10, SN74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS526A – AUGUST 1995 – REVISED APRIL 1996 D D D SN54ACT10 . . . J OR W PACKAGE SN74ACT10 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54ACT11, SN74ACT11 TRIPLE 3-INPUT POSITIVE-AND GATES SCAS531A – AUGUST 1995 – REVISED APRIL 1996 D D D SN54ACT11 . . . J OR W PACKAGE SN74ACT11 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54ACT11, SN74ACT11 TRIPLE 3-INPUT POSITIVE-AND GATES SCAS531A – AUGUST 1995 – REVISED APRIL 1996 D D D SN54ACT11 . . . J OR W PACKAGE SN74ACT11 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54ACT11, SN74ACT11 TRIPLE 3-INPUT POSITIVE-AND GATES SCAS531A – AUGUST 1995 – REVISED APRIL 1996 D D D SN54ACT11 . . . J OR W PACKAGE SN74ACT11 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted