TTL 3 INPUT AND Search Results

DC-3000

Abstract: SW-312
Contextual Info: GaAs SPDT Reflective Switch DC - 3 GHz with TTL/CMOS Control Input SW-312 V2.00 Features ● ● ● ● ● CR-9 Integral Silicon Driver Ultra Low Power Consumption TTL and CMOS Input Compatible Fast Switching Speed: 7 ns Typical Surface Mount Package 0.050 1.27

DM74ALS27

Abstract: 74ALS DM74ALS DM74ALS27M DM74ALS27N M14A N14A
Contextual Info: DM74ALS27 Triple 3-Input NOR Gate n Advanced oxide-isolated, ion-implanted Schottky TTL process n Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart n Improved AC performance over Schottky and low power Schottky counterparts

10H350

Abstract: j201 Application Note J201 MC10H350 SY10H350 SY10H350JC SY10H350JCTR SY10H350JZ SY10H350JZTR
Contextual Info: Micrel, Inc. PECL-to-TTL TRANSLATOR DESCRIPTION FEATURES • ■ ■ ■ The SY10H350 consists of 4 translators with differential inputs and TTL outputs. The 3-state outputs can be disabled by applying a HIGH TTL logic level on the common OE input. The SY10H350 is designed to be used primarily in

Contextual Info: ACTS138MS Semiconductor Radiation Hardened TTL Input, 3-to-8 Line Decoder/Demultiplexer December 1997 Features Description • QM L Qualified Per MIL-PRF-38535 Requirements The Radiation Hardened ACTS138MS is an Inverting 3-to-8 Line Decoder/Demultiplexer with three TTL level binary

1016E

Abstract: 1032E 0163B ispLSI1000
Contextual Info: 1000 and 1000E Family Architectural Description input, registered input, latched input, output or bidirectional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output

"XOR Gate"

Abstract: 1032E 1016E 1048E 1000EA 0163B ispLSI1000
Contextual Info: 1000EA, 1000E and 1000 Family Architectural Description input, registered input, latched input, output or bidirectional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output

Contextual Info: LS TTL DN74LS Series DN74LS12 DN74LS12 Triple 3 - input P o sitiv e NAND Gates with Open Collector Outputs P-1 • Description DN74LS12 contains three 3-input positive isolation NAND gate circuits with open collector outputs. ■ Features • • • “Wired” AND capability

74HC27

Abstract: dhvqfn14 74HC27N 74HC27BQ 74HC27D 74HC27DB 74HC27PW 74HCT27 JESD22-A114E HCT273
Contextual Info: 74HC27; 74HCT27 Triple 3-input NOR gate Rev. 03 — 7 January 2008 Product data sheet 1. General description The 74HC27; 74HCT27 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL LSTTL . The 74HC27; 74HCT27 provides the 3-input NOR function.

hct244a

Abstract: HCT241A T244A 1A48C HC74HC
Contextual Info: TOSHIBA TC74HCT240AP/AF/AFW TC74HCT241AP/AF TC74HCT244AP/AF/AFW Octal Bus Buffer with TTL Input Level TC74HCT240 Inverted, 3-State Outputs TC74HCT241 Non-lnverted, 3-State Outputs TC74HCT244 Non-lnverted, 3-State Outputs The TC74HCT240A, HCT241A and HCT244A are high

DDU4F

Abstract: DDU4F-5004 DDU4F-5006 DDU4F-5008 DDU4F-5010 DDU4F-5012 DDU4F-5016 DDU4F-5020 DDU4F-5025 DDU4F-5030
Contextual Info: DDU4F data 3  delay devices, inc. 5-TAP, TTL-INTERFACED FIXED DELAY LINE SERIES DDU4F FEATURES PACKAGES • • • • • Five equally spaced outputs Fits standard 14-pin DIP socket Low profile Auto-insertable Input & outputs fully TTL interfaced & buffered

circuit diagram of 8-1 multiplexer design logic

Abstract: 74hc257 DIP16 package SSOP16 package CMOS Quad 2-Input NOR Gate input Equivalent Circuit with transistor 3-State 74HC257D 74HC257DB 74HC257N 74HC258
Contextual Info: 74HC257; 74HCT257 Quad 2-input multiplexer; 3-state Rev. 03 — 20 September 2005 Product data sheet 1. General description The 74HC257; 74HCT257 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . The 74HC257; 74HCT257 has four identical 2-input multiplexers with 3-state outputs,

NL27WZ16DTT1G

Abstract: A114 A115 C101 JESD22 NL27WZ16 marking code 46 tsop-6
Contextual Info: NL27WZ16 Dual Buffer The NL27WZ16 is a high performance dual buffer operating from a 1.65 to 5.5 V supply. At VCC = 3 V, high impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance.

DDU8F

Abstract: DDU8F-5004 DDU8F-5006 DDU8F-5008 DDU8F-5010 DDU8F-5012 DDU8F-5016 DDU8F-5020 DDU8F-5025 DDU8F-5030
Contextual Info: DDU8F data 3  delay devices, inc. 5-TAP, TTL-INTERFACED FIXED DELAY LINE SERIES DDU8F FEATURES • • • • • • PACKAGES Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully TTL interfaced & buffered

Contextual Info: NL27WZ16 Dual Buffer The NL27WZ16 is a high performance dual buffer operating from a 1.65 to 5.5 V supply. At VCC = 3 V, high impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance.

SO-140

Abstract: DN74LS12
Contextual Info: DN74LS1 2 LS TTL DN74LS Series DN74LS12 T rip le 3 - input P o sitiv e NAND G ates with Open C ollector Outputs • Description P-1 DN 74LS12 contains three 3-input positive isolation NAND gate circuits w ith open collector outputs. ■ Features • •

751A-02

Abstract: 74f64 motorola
Contextual Info: MC54/74F64 4-2-3-2-INPUT AND-OR-INVERT GATE 4-2-3-2-INPUT AND-OR-INVERT GATE FAST SCHOTTKY TTL VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 14 7 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

PDU138

Abstract: PDU138-1 PDU138-10 PDU138-12 PDU138-15 PDU138-2 PDU138-20 PDU138-5
Contextual Info: PDU138 data 3  delay devices, inc. 3-BIT PROGRAMMABLE DELAY LINE SERIES PDU138 FEATURES • • • • • • • PACKAGES Digitally programmable in 8 delay steps Monotonic delay-versus-address variation Precise and stable delays Input & outputs fully TTL interfaced & buffered

Contextual Info: fl} PERICOM 3.3V Fast CMOS Buffer/Clock Driver Product Features: • • • • • • • • Product Description: 3 ,3V version of PI49FCT804T Low output skew: 0.8 ns Clock busing with 3-state control TTL input and output levels, reducing problematic "ground bounce"

J11B1

Abstract: J9B1 10A1 10B1 10B2 10B3 11A1 11B1 11B3 SN74CBT16214
Contextual Info: SN74CBT16214 3-T0-1 BUS-SELECT SWITCH SCOS008B-MAY 1 9 9 3 - REVISED FEBRUARY 1995 Switch Connection Between Two Ports 5 -Q TTL-Compatible input and Output Levels Packaged in Plastic 300-mil Shrink Small-Outline DL and Thin Shrink Small-Outiine (DGG) Packages

ICE 3BO 365

Abstract: SN54ABTE16246 SN74ABTE16246 VME64
Contextual Info: SN54ABTE16246, SN74ABTE16246 11-BIT INCIDENT-WAVE SWITCHING BUS-CONTROL TRANSCEIVERS WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS SC B S 22 7 B -JU L Y 1 9 9 3 - REVISED AUGUST 1994 Supports the VME64 ETL Specification Reduced, TTL-Compatible, Input Threshold Range

DN74LS10

Abstract: MA161
Contextual Info: I LS TTL DN74LS Series DN74LS10 DN74LS10 T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption P,j = 6mW typical High speed ( tpd = 10ns typical)

DN74LS10

Abstract: MA161
Contextual Info: LS TTL DN74LS Series DN74LS10 DN74LS10 bio74-LSto T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption Pd = 6mW typical High speed ( tpd = 10ns typical)

IC SN74HC

Abstract: SN74HCTOO SN74HC
Contextual Info: SN54HCT00, SN74HCT00 QUADRUPLE 2-INPUT POSITIVE NANO GATES D 3 2 4 3 , NOVEMBER 1968 Inputs are TTL-Voftage Compatible S N 54H C T00 S N 74H C T00 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil

Contextual Info: ME RR I M A C INDUSTRIES INC MbE D m bOGMbB'i 0 0 0 2 0 3 3 Merrimac 4 m m iljZ JTF-2F series QUADRAPHASE MODULATORS Integrated TTL Drivers O DATA INPUT > BI-PH ASE MODULATOR 1 90 » QUAD HYBRID R F INPUT o— CARRIER DATA 1 INPUT o- IN -PH A S E POWER