TRAP FLOATING POINT Search Results

16 BIT ALU design structural

Contextual Info: Chapter 2 TurboSPARC Architecture 2.1 INTEGER UNIT AND FLOATING POINT CONTROLLER The integer unit IU and floating point control (FPC) are merged into a 9-stage pipeline. Below are some of the features of the IUFPC. • 9 stage instruction pipeline. • No branch folding. Branch instructions (taken/non-taken) execute in one cycle.

FGT 313

Contextual Info: in te i ¡860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for

Intel i860

Contextual Info: INTEL CORP UP/PRPHLS bflE » • 4ñ2bl7S Dia^flSb in te i i860 XR 64-BIT MICROPROCESSOR ■ Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per

NS32016

Abstract: NS32032 NS32381V-15 10b38 NS32381 NS32008 NS32081 NS32381U NS32381V-30 NS32GX320
Contextual Info: April 1991 NS32381-15 NS32381-20 NS32381-25 NS32381-30 Floating-Point Unit General Description The NS32381 is a second generation CMOS floating-point slave processor that is fully software compatible with its forerunner the NS32081 FPU The NS32381 FPU functions

UT699

Contextual Info: Aeroflex Colorado Springs Errata UT699 LEON 3FT Microprocessor GRFPU/GPC Floating Point Errata Overview This errata document covers all known bugs in the GRFPU/FPC Floating Point Unit present in GRLIB revision 1996, affecting the UT699 LEON 3FT Microprocessor.

XO-31

Abstract: AAD00-AAD04 wtl3164 weitek NS32580-30 NS32081
Contextual Info: PRELIMINARY NS32580-20/NS32580-25/NS32580-30 Floating Point Controller G eneral Description The NS32580 Floating-Point Controller FPC is an interface device designed to couple the NS32532 Microprocessor with the Weitek WTL 3164 Floating-Point Data Path (FPDP).

mb86901

Contextual Info: F U J IT S U High Performance 32-Bit RISC Processor SPARC FEATURES • Architecture supports scalability towards faster technologies • Address presentation which supports highperformance cache • 15 times V A X ™ 11/780 equivalent MIPS typical performance

ieee floating point alu in vhdl

Abstract: ERC32 ieee floating point vhdl ieee floating point multiplier vhdl SPARC RT TSC691E TSC692E TSC693E RAM SEU ieee 32 bit floating point multiplier
Contextual Info: SPARC Processor for SPACE Applications TEMIC Semiconductors is offering a SPARC RT Radiation Tolerant processor, based on SPARC V7 architecture, for space applications, consisting of three devices: integer unit (IU), the TSC691E, floating point unit (FPU), the TSC692E,

SPARC V7.0

Contextual Info: Temic Semiconductors TSC692E Floating Point Unit User’s Manual for Embedded Real time 32-bit Computer ERC32 for SPACE Applications Temic Semiconductors TSC692E Table of Contents 1. Introduction. 1

mc6839

Abstract: MC6809E M6809 MC68B39L MC6809 motorola 6809 instruction set opcoa S3F80 MC68B39P ERES CGL
Contextual Info: MC6839 M O T O R O LA Advance Information M OS N -C H A N N E L , S IL IC O N -G A T E } FLOATING-POINT ROM The M C6839 standard p ro d u c t ROM provides flo a tin g p o in t capa bility for the M C6809 or MC6809E M PU . The M C6839 im plem e nts th e entire

erc32 trap 0x61

Abstract: Cy7C601 ERC32 CB123 TSC691E TSC692E TSC693E tbr 3516 SPARC V7.0
Contextual Info: TSC691E Integer Unit User’s Manual for Embedded Real time 32–bit Computer ERC32 for SPACE Applications TSC691E Table of contents 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

AXP 223

Abstract: 000D 21068 EV45 21164a Alpha 21164PC
Contextual Info: Alpha Architecture Handbook Order Number EC–QD2KB–TE Revision/Update Information: This is Version 3 of the Alpha Architecture Handbook. The changes and additions in this book are subsequent to the Alpha AXP Architecture Reference Manual, Second Edition, and the Alpha AXP Architecture Handbook, Version 2.

NS32*32

Abstract: 32C032 NS32081 C1995 NS32082 NS32202 NS32C032-10 NS32C032-15 916070 32C201
Contextual Info: NS32C032-10 NS32C032-15 High-Performance Microprocessors General Description Features The NS32C032 is a 32-bit virtual memory microprocessor with a 16-MByte linear address space and a 32-bit external data bus It has a 32-bit ALU eight 32-bit general purpose

ERC32

Abstract: CB123 CY7C601 TSC691E TSC692E TSC693E FPU-TSC692E erc32 trap 0x61 TMS 3529 A1191
Contextual Info: TSC691E Integer Unit User’s Manual for Embedded Real time 32–bit Computer ERC32 for SPACE Applications TSC691E Table of contents 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

NS32C016D-10

Abstract: NS32082 C1995 NS32202 NS32C016-10 NS32C016-15 sample 32082 NS32081
Contextual Info: July 1989 NS32C016-10 NS32C016-15 High-Performance Microprocessors General Description Features The NS32C016 is a 32-bit CMOS microprocessor with TTL compatible inputs The NS32C016 has a 16M byte linear address space and a 16-bit external data bus It is fabricated with National Semiconductor’s advanced CMOS process

CY7C157A

Contextual Info: CY7C601A CYPRESS SEMICONDUCTOR 32-Bit RISC Processor — Registers can be used as eight win­ dows of 24 registers each for low procedure overhead — Registers can also be used as regis­ ter banks for fast context switching Features • Reduced Instruction Set Computer

90c61

Abstract: Trap floating point
Contextual Info: 4 CIE D MATRA M H S • SñbñMSb 00023^^ _ F p B A f C lllììlilll I w T B W 414 «M M H S _ " 3 8 January 1991 90C601 DATA SHEET_ 32-BIT RISC PROCESSOR FEATURES ■ REDUCED INSTRUCTION SET COMPUTER RISC ARCHITECTURE - SIMPLE FORMAT INSTRUCTIONS

Contextual Info: CYPRESS MbE D SEMICONDUCTOR ^ asa-Ttta oao74t.i T - M i- n - 3 8 CYPRESS SEMICONDUCTOR • Reduced Instruction Set Computer RISC Architecture — Simple format instructions — M ost instructions execute in a single cycle • Very high performance — 25-, 33-, and 40-MHz clock speeds

300-900MHz

Abstract: sparc v8
Contextual Info: TurboSPARC Highly Integrated 32-bit RISC Microprocessor DATASHEET NOVEMBER 1996 • The Fujitsu TurboSPARC Microprocessor is a high frequency, highly integrated single-chip CPU providing balanced integer and floating point performance. The TurboSPARC microprocessor is an implementation of the SPARC

AN701

Abstract: 3F80 0M22
Contextual Info: MICROCONTROLLER PRODUCTS AN701 SP floating point math with XA Author: Santanu Roy Philips Semiconductors 1995 Jul 28 Philips Semiconductors Application note SP floating point math with XA AN701 Author: Santanu Roy, MCO Applications Group, Sunnyvale, California

AN701

Abstract: ieee 32 bit floating point multiplier 3F80
Contextual Info: MICROCONTROLLER PRODUCTS AN701 SP floating point math with XA Author: Santanu Roy Philips Semiconductors 1995 Jul 28 Philips Semiconductors Application note SP floating point math with XA AN701 Author: Santanu Roy, MCO Applications Group, Sunnyvale, California

ARM coprocessor

Abstract: ARM FPA ARM processor Basic ARM block diagram SFM 27 WFs transistor 110P ARM7500FE clock arithmetic FPSR
Contextual Info: 1 8 11 The FPA Coprocessor Macrocell This chapter gives an overview of the FPA coprocessor macrocell. 8.1 Overview 8-2 8.2 FPA Functional Blocks 8-3 8.3 FPA Block Diagram 8-5 ARM7500FE Data Sheet ARM DDI 0077B Open Access - Preliminary 8-1 The FPA Coprocessor Macrocell

AN1267

Abstract: RISC semaphore embedded c programming of fibonacci series
Contextual Info: Order this document by AN1267/D Microprocessor and Memory Technologies Group AN1267 Application Note PowerPC 603 Hardware Interrupt Latency In Embedded Applications By Wendell Smith, Paul Nelson, and Amy Dyson, High Performance Embedded Systems The PowerPC™ 603 microprocessor is a RISC design, achieving a high level of performance using instruction

COPROCESSOR

Abstract: MC68EC030 opcode mc68851 motorola 68020 manual Motorola 68030 opcodes Motorola 68030 motorola 68000 motorola 68020 M68030 control unit of a processor 68030
Contextual Info: MOTOROLA M68000 FAMILY Programmer’s Reference Manual Includes CPU32 Instructions MOTOROLA INC., 1992 TABLE OF CONTENTS Paragraph Number Title Page Number Section 1 Introduction 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.2 1.2.1 1.2.2 1.2.2.1 1.2.2.2 1.2.3 1.2.3.1