TRANSISTOR GW 93 H Search Results

Contextual Info: w m m x KD421K10 Powerex, Inc., 200 Hillis Street, Youngwood, Pennsylvania 15697-1800 412 925-7272 D U d l D S r liflQ tO n Transistor Module 100 Amperes/1000 Volts OUTLINE DRAWING Description: The Powerex Dual Darlington Transistor Modules are high power

transistor GW 93 H

Abstract: 100-PIN
Contextual Info: LH51V1032C4 PRELIMINARY 32K x 32 Pipelined Burst SRAM +3.3 V Supply, Fully Registered Inputs, Outputs, and Burst Counter FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 8 and 9 ns The Sharp Synchronous SRAM family employs highspeed, low-power CMOS designs using a thin-film transistor memory cell. Sharp SRAMs are fabricated using

MCache

Abstract: PBSRAM IDT71F432 IDT71F432S66 IDT71F432S75
Contextual Info: FEATURES: • • • • • • • • • • Uses IDT's Fusion Memory technology 66 and 75 MHz speed grades 3-1-1-1 Pipelined Burst Read 3-1-1-1 Pipelined Burst Write 3-1-1-1-1-1-1-1. extended pipelined operation Refresh overhead consumes less than 0.5% of cycles

362-0 transistor

Abstract: PBSRAM MCache
Contextual Info: ADVANCE INFORMATION IDT71F632 64Kx32 Fusion Memory SYNCHRONOUS CACHE RAM Integrated Device Technology, Inc. • • • • • • • • • Uses IDT's Fusion Memory technology 66 and 75 MHz speed grades 3-1-1-1 Pipelined Burst Read 3-1-1-1 Pipelined Burst Write

IDT71F432

Abstract: IDT71F432S66 IDT71F432S75
Contextual Info: PRELIMINARY IDT71F432 32K x 32 Fusion Memory SYNCHRONOUS PIPELINED CACHE RAM Integrated Device Technology, Inc. FEATURES: performance of SRAM with the cost structure of DRAM. It is fundamentally compatible with standard PBSRAM, with additional features to accommodate the internal DRAM operation

PBSRAM

Abstract: IDT71F432 IDT71F432S66 IDT71F432S75
Contextual Info: FEATURES: • • • • • • • • • • Uses IDT's Fusion Memory technology 66 and 75 MHz speed grades 3-1-1-1 Pipelined Burst Read 3-1-1-1 Pipelined Burst Write 3-1-1-1-1-1-1-1. extended pipelined operation Refresh overhead consumes less than 0.5% of cycles

2N7805

Abstract: gw 340 diode t03 package transistor pin configuration 32N03 DTG2400 DTG-2400 2N2144A 2N1100 2N126 2n228 transistor
Contextual Info: CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features The CY7C1339 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when V DDq=2.5V. * Supports 100-MHz bus fo r Pentium and PowerPC operations w ith zero w ait states

CY7C1361C

Abstract: CY7C1363C Intel Core
Contextual Info: CY7C1361C/CY7C1363C 9-Mbit 256 K x 36/512 K × 18 Flow-through SRAM 9-Mbit (256 K × 36/512 K × 18) Flow-through SRAM Features Functional Description • Supports 100, 133 MHz bus operations ■ Supports 100 MHz bus operations (Automotive) ■ 256 K × 36/512 K × 18 common I/O

transistor GW 93 H

Abstract: 362-0 transistor 71F63
Contextual Info: 64 K x 32 Fusion Memory SYNCHRONOUS CACHE RAM ADVANCE INFORMAflON IDT71F632 Integrated Device Technology, Inc. FEATURES: • • • • • • • • • Uses IDT's Fusion Memory™ technology 66 and 75 MHz speed grades 3-1-1-1 Pipelined Burst Read 3-1-1-1 Pipelined Burst Write

Contextual Info: CY7C1480V33 CY7C1482V33 CY7C1486V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined Sync SRAM 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM Features Functional Description[1] • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz

Contextual Info: CY7C1480V33 CY7C1482V33 CY7C1486V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined Sync SRAM 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM Features Functional Description[1] • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz

NE76038

Contextual Info: LOW NOISE L TO Ku-BAND Ga As MESFET FEATURES NE76038 NOISE FIGURE & ASSOCIATED GAIN vs. FREQUENCY V ds = 3 V, I ds = 10 mA LOW NOISE FIGURE: 1.8 dB typical at 12 GHz 4 HIGH ASSOCIATED GAIN: 7.5 dB typical at 12 GHz 24 3.5 21 Ga 18 3 Lg = 0.3 im, Wg = 280 )im

Contextual Info: 64K X 32 Fusion Memory SYNCHRONOUS CACHE RAM FEATURES: . performance of SRAM with the cost structure of DRAM. It is fundamentally compatible with standard PBSRAM, with addi­ tional features to accommodate the internal DRAM operation of the memory. These additional features are defined so that

Contextual Info: CY7C1480V33 72-Mbit 2 M x 36 Pipelined Sync SRAM 72-Mbit (2 M × 36) Pipelined Sync SRAM Functional Description Features • Supports bus operation up to 200 MHz ■ Available speed grades are 200 and 167 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1444AV33 CY7C1445AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz

Contextual Info: CY7C1480V33 72-Mbit 2 M x 36 Pipelined Sync SRAM 72-Mbit (2 M × 36) Pipelined Sync SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades are 200 and 167 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1480V33 72-Mbit 2 M x 36 Pipelined Sync SRAM 72-Mbit (2 M × 36) Pipelined Sync SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades are 200 and 167 MHz ■ Registered inputs and outputs for pipelined operation

1ZI1

Abstract: pk100-1 PK1001
Contextual Info: í:jW>s\í> ^dt Integrated De\/ice Technology, Inc. 32K x 32 MCache SYNCHRONOUS PIPELINED CACHE RAM FEATURES: • Uses IDT's Fusion Memory technology • 66 and 75 MHz speed grades • 3-1-1-1 Pipelined Burst Read • 3-1-1-1 Pipelined Burst Write • 3-1-1-1-1-1-1-1. extended pipelined operation

U4226B

Abstract: dcf antenna U4226 DCF 77 simple SL 100 NPN Transistor dcf77 receiver pon loop antenna dcf dcf ferrite antenna 77.5 khz DCF77
Contextual Info: U4226B Time Code Receiver Description The U4226B is a bipolar integrated straight through receiver circuit in the frequency range of 40 to 80 kHz. The device is designed for radio controlled clock applications. Features D D D D Very low power consumption D Only a few external components necessary

LOW khz receiver 77,5kHz

Abstract: time code receiver 60khz msf SL 100 NPN Transistor dcf ferrite antenna dcf77 receiver dcf77 transistor E 13007 dcf CLOCK E 13007 equivalent of SL 100 NPN Transistor
Contextual Info: U4226B Time-Code Receiver with TC Output Description The U4226B is a bipolar integrated straight-through receiver circuit in the frequency range of 40 to 80 kHz. The device is designed for radio-controlled clock applications. Features D D D D Very low power consumption

dcf77

Abstract: dcf77 antenna loop p q1a U4226b dcf ferrite antenna dcf77 receiver E 13007 simple SL 100 NPN Transistor SSO20 U4226B-MFS
Contextual Info: U4226B Time-Code Receiver with TC Output Description The U4226B is a bipolar integrated straight-through receiver circuit in the frequency range of 40 to 80 kHz. The device is designed for radio-controlled clock applications. Features D D D D Very low power consumption

Contextual Info: 32K x 32 Fusion Memory SYNCHRONOUS PIPELINED CACHE RAM FEATURES: performance of SRAM with the cost structure of DRAM. It is fundamentally compatible with standard PBSRAM, with addi­ tional features to accommodate the internal DRAM operation of the memory. These additional features are defined so that

SKM 40 GD 121 D

Abstract: SKM 40 GD 101 D skm 40 gd 121 skm 200 gb 122 d skm 75 gb 101 d skm 150 gb 122 SKM 25 GD IGBT cross reference semikron skm 40 gd 121 SKM 300 GA 102 D Semitrans M SKm 100 ga 121 d
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simple SL 100 NPN Transistor

Abstract: wwvb DCF77 T4225B T4225B-MC T4225B-MF T4225B-MW dcf receiver time code receiver dcf
Contextual Info: T4225B Time Code Receiver Description The T4225B is a bipolar integrated straight through receiver circuit in the frequency range of 40 to 80 kHz. The device is designed for radio controlled clock applications. Features D D D D Very low power consumption D Only a few external components necessary