TQFP 80 SLUG UP TOP Search Results

PHD64

Abstract: land pattern for vsop 8 pins land pattern for vsop DCA56 PFC80 PZT10 DED28 DFD64 DAP38 PWD14
Contextual Info: PowerPAD - A Method To Create Thermally Enhanced Plastic Package Solutions for Semiconductors Milton L. Buschbom, Mark Peterson, Shih-Fang Chuang, David Kee, and Buford Carter Texas Instruments, Incorporated Dallas, Texas f = switching frequency in Hz N = number of gates switched/clock cycle

JESD51-8

Abstract: JESD51-2 JEDEC JESD51-8 qfn 44 PACKAGE footprint 9mm surface mount package dimensions FREESCALE PACKING jesd51 8 JEDEC-STD-020 JEDEC-STD020 tqfp 44 PACKAGE footprint
Contextual Info: Freescale Semiconductor, Inc. ANALOG ICs INTEGRATED SOLUTIONS Freescale Semiconductor, Inc. PACKAGING Robust packaging is a key technology component of Analog Products. Motorola puts solutions together in single packages to accomodate power and high voltages.

TQFP-EP

Abstract: AD9276BSVZ IQ demodulator octal ultrasound vga ANSI-644
Contextual Info: Octal LNA/VGA/AAF/ADC and CW I&Q Demodulator AD9276 Preliminary Technical Data FEATURES 8 channels of LNA, VGA, AAF, ADC and I&Q Demodulator Low noise preamplifier LNA Input-referred noise = 0.75 nV/√Hz (gain = 21.3 dB) @ 5 MHz typical SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB

mps 0940

Abstract: jedec footprint MO-220 VHHD-2 32-lead TQFP TQFP 80 slug up top programmable delay JEDEC Drawing MO-220 7mm tqfp 64 pcb land pattern
Contextual Info: FemtoClock LVDS Programmable Delay Line ICS854S295I-25 DATA SHEET General Description Features The ICS854S295I-25 is a high performance LVDS Programmable Delay Line. The delay can vary from 1.6ns to 16.0ns in 10ps steps. The ICS854S295I-25 is characterized to operate from a 2.5V power

Contextual Info: ICS843S050DI-02 FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843S050DI-02 is a 10 output 3.3V LVPECL ICS Synthesizer optimized to generate micro-processor HiPerClockS™ reference clock frequencies and is a member of the

DA472

Contextual Info: PRELIMINARY TECHNICAL DATA a 12-Bit, 170 MSPS 3.3V A/D Converter Preliminary Technical Data AD9430 FEATURES SNR = 66dB @ Fin up to 65MHz at 170Msps ENOB of 10.3 @ Fin up to 65MHz at 170 Msps -1dBFs SFDR = -80dBc @ Fin up to 65MHz at 170Msps (1dBFs) Excellent Linearity:

MPS 0633

Abstract: mps 0646
Contextual Info: Crystal-to-LVDS Clock Synthesizer ICS844625I DATA SHEET General Description Features The ICS844625I is a high frequency clock generator. The ICS844625I uses an external 25MHz crystal to synthesize 312.5MHz, 156.25MHz and 125MHz clocks. The ICS844625I has excellent cycle-to-cycle and RMS period jitter performance.

Contextual Info: DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER I CS8 7 3 9 9 6 GENERAL DESCRIPTION FEATURES The ICS873996 is a Zero Delay/Multiplier/Divider ICS with hitless input clock switching capability and a HiPerClockS member of the HiPerClockS™ family of low jitter/

ICS873996AY

Abstract: ICS873996AYT VCO 10G ICS873996 48-PIN ICS873996AYLF ICS873996AYLFT MS-026 TQFP 80 slug up top Nippon capacitors
Contextual Info: ICS873996 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER GENERAL DESCRIPTION FEATURES The ICS873996 is a Zero Delay/Multiplier/Divider ICS with hitless input clock switching capability and a HiPerClockS member of the HiPerClockS™ family of low jitter/

DIP10

Abstract: DIP12 GD16523 GD16523-100BA
Contextual Info: 2.5 Gbit/s 16:1 Multiplexer GD16523 an Intel company Preliminary General Information Features The GD16523 is a multirate STM 1/4/16 plus 1.25 Gbit/s bit-rates 16:1 re-timing multiplexer with jitter clean-up capability. The VCXO reference clock input is differential and the frequency is selectable

DIP10

Abstract: DIP12 GD16523
Contextual Info: an Intel company 2.5 Gbit/s 16:1 Multiplexer GD16523 General Information Features The GD16523 is a multirate STM 1/4/16 plus 1.25 Gbit/s bit-rates 16:1 re-timing multiplexer with jitter clean-up capability. The VCXO reference clock input is differential and the frequency is selectable

Contextual Info: DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER I CS8 7 3 9 9 5 GENERAL DESCRIPTION FEATURES The ICS873995 is a Zero Delay/Multiplier/Divider ICS with hitless input clock switching capability and a HiPerClockS member of the HiPerClockS™ family of low jitter/

Contextual Info: 2.5 Gbit/s 16:1 Multiplexer GD16523 Preliminary General Information Features The GD16523 multiplexes sixteen data inputs into a single data output, the bit rates of the inputs are selectable see table below . The data inputs are forward clocked by the differential input (DCLKP / DCLKN).

ICS873995

Abstract: 48-PIN ICS873995AY MS-026 VCO 10G
Contextual Info: ICS873995 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER GENERAL DESCRIPTION FEATURES The ICS873995 is a Zero Delay/Multiplier/Divider ICS with hitless input clock switching capability and a HiPerClockS member of the HiPerClockS™ family of low jitter/

614.4MHZ

Contextual Info: PRELIMINARY ICS813076I FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR WIRELESS INFRASTRUCTURE APPLICATIONS GENERAL DESCRIPTION FEATURES The ICS813076I is a member of the HiperClocks ICS family of high performance clock solutions from IDT. HiPerClockS

TQFP-EPAD-64

Abstract: tqfp 64 pcb land pattern 4051N ICS843002BY-31
Contextual Info: FemtoClock VCXO Based Frequency Translator/Jitter Attenuator ICS843002-31 NRND PRELIMINARY DATA SHEET GENERAL DESCRIPTION FEATURES This monolithic device is a high-performance, PLL-based synchronous clock generator and jitter attenuation circuit. The ICS843002-31 contains two clock multiplication stages that

agilent signal generator

Abstract: ICS853S6111I ICS853S6111AYI IFR2042 MS-026
Contextual Info: Low Voltage, 1-to-10, Differential-to- ICS853S6111I 2.5V, 3.3V LVPECL/ECL Fanout Buffer DATA SHEET General Description Features The ICS853S6111I is a low skew 1-to-10 Differential Fanout Buffer, designed with clock distribution in mind, accepting two clock sources

ICS853S6111I

Abstract: 8133A ICS853S
Contextual Info: Low Voltage, 1-to-10, Differential-to- 2.5V, 3.3V LVPECL/ECL Fanout Buffer ICS853S6111I DATA SHEET Product Discontinuance Notice – Last Time Buy Expires on 1/31/2014 General Description Features The ICS853S6111I is a low skew 1-to-10 Differential Fanout Buffer,

Contextual Info: Low Voltage, 1-to-10, Differential-to- 2.5V, 3.3V LVPECL/ECL Fanout Buffer ICS853S6111I DATA SHEET Product Discontinuance Notice – Last Time Buy Expires on 1/31/2014 General Description Features The ICS853S6111I is a low skew 1-to-10 Differential Fanout Buffer,

tqfp 64 pcb land pattern

Contextual Info: ICS813078I FEMTOCLOCKS VCXO-PLL FREQUENCY GENERATOR FOR WIRELESS INFRASTRUCTURE EQUIPMENT General Description Features The ICS813078I is a member of the HiperClocks family of high performance clock solutions from IDT. HiPerClockS™ The ICS813078I a PLL based synchronous clock

Frequency Generator 1MHz

Abstract: Frequency Generator 10kHz Frequency Generator 10MHz Frequency Generator 1KHZ QCN-45 smd marking QY TRANSISTOR SMD N2 3j NB 3H SMD transistor qa1 smd footprint jedec MS-026 TQFP
Contextual Info: ICS813078I FEMTOCLOCKS VCXO-PLL FREQUENCY GENERATOR FOR WIRELESS INFRASTRUCTURE EQUIPMENT General Description Features The ICS813078I is a member of the HiperClocks family of high performance clock solutions from IDT. HiPerClockS™ The ICS813078I a PLL based synchronous clock

FAGD16524100BA

Abstract: DO15 GD16524 STM16 STM-16 intel 7882
Contextual Info: 2.5 Gbit/s Clock and Data Recovery and 1:16 DeMUX GD16524 an Intel company General Description Features The CDR contains all circuits needed for reliable acquisition and lock of the VCO phase to the incoming data-stream. The electrical input sensitivity is better

intel 7882

Abstract: 31 anl DO15 GD16524 STM16 STM-16
Contextual Info: 2.5 Gbit/s Clock and Data Recovery and 1:16 DeMUX GD16524 an Intel company General Description Features The CDR contains all circuits needed for reliable acquisition and lock of the VCO phase to the incoming data-stream. The electrical input sensitivity is better

intel 7882

Abstract: DO15 GD16524 STM16 STM-16 GD16524-100BA
Contextual Info: 2.5 Gbit/s Clock and Data Recovery and 1:16 DeMUX GD16524 an Intel company Preliminary General Description Features The CDR contains all circuits needed for reliable acquisition and lock of the VCO phase to the incoming data-stream. The electrical input sensitivity is better