TQFP 144 PACKAGE FOOTPRINT Search Results

XC95144XL-10TQG100C

Abstract: XC95144XL-10TQ100I XC95144XL-10CSG144C XC95144XL-10TQ144I XC95144XL-5-TQ100 XC95144XL-10TQG144C xc95144xl XC95144XL-10TQG100I XC95144XL-7TQ100C TQFP 100 PACKAGE footprint
Contextual Info: XC95144XL High Performance CPLD R DS056 v2.0 April 3, 2007 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins)

atmel 216

Abstract: TQFP 132 PACKAGE TQFP216 BGA-121
Contextual Info: Packaging Introduction Atmel pairs its high-performance silicon with packages, custom designed for the company’s gate arrays. Atmel offers our gate arrays in ceramic and plastic packages. Atmel’s plastic through hole and surface mount packages come in a

xc95144xl tq144

Contextual Info: XC95144XL High Performance CPLD DS056 v1.3 October 13, 2000 5 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 222 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins)

xc9572xl pin configuration

Abstract: XC9572XL XC9572XL-10PCG44C XC9572XL-10CS48I XC9572XL-10VQG44C XC9572XL-7TQ100C XC9572XL-10PC44C xc9572xl-10PCG44C pin XC9572XL-7PCG44C XC9572XL-5TQG100C
Contextual Info: XC9572XL High Performance CPLD R DS057 v2.0 April 3, 2007 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.2, September 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

LCMXO2-256 pinout

Abstract: LCMXO2-2000 pinout
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.1, June 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

ispMACH 4A5

Abstract: TQFP 44 PACKAGE footprint footprint tqfp 208 footprint plcc 208 footprint pqfp 208 lattice m4a3 TQFP 48 PACKAGE footprint footprint TQFP 48 ispMACH M4A3 100-pin BGA
Contextual Info: Introduction to ispMACH 4A Family TM Introduction The ispMACH 4A Family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device CPLD solution of easy-to-use silicon products and software tools. The

TQFP 44 PACKAGE footprint

Abstract: TQFP 100 PACKAGE footprint footprint tqfp 208 TQFP 144 PACKAGE footprint ispMACH 4A5 TQFP-100 footprint footprint plcc 208 TQFP 100 footprint footprint pqfp 208 ispMACH M4A3
Contextual Info: Introduction to ispMACH 4A Family TM Introduction The ispMACH 4A Family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device CPLD solution of easy-to-use silicon products and software tools. The

MACHXO2 7000 pinout

Abstract: MachXO2-4000
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.3, December 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.1, June 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: XC95144XV High-Performance CPLD R DS051 v2.0 January 25, 2001 1 Advance Product Specification Features Power Estimation • 144 macrocells with 3,200 usable gates • Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins)

Contextual Info: LSI CSP • CSP Chip Size Package •CSP The FBGA (commonly known as CSP) has an area array terminal structure with solder balls on the bottom, to give it a near chip-size footprint. This high-density, compact and low-profile package technology will greatly help in the design of compact mobile equipment, such as mobile phones and

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.0, January 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.0, January 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

XCR3128XL-10VQG100C

Abstract: XCR3128XL-10CS144I XCR3128XL-10TQG144I XCR3128XL-7VQG100C vqfp package pinout XCR3128XL-10CSG144C XCR3128XL-10VQG100I XCR3128XL-10VQ100I XCR3128XL-7TQG144C XCR3128XL-10VQ100C
Contextual Info: XCR3128XL 128 Macrocell CPLD R DS016 v2.6 March 31, 2006 14 Product Specification Features Description • Low power 3.3V 128 macrocell CPLD • 5.5 ns pin-to-pin logic delays The CoolRunner XPLA3 XCR3128XL device is a 3.3V 128 macrocell CPLD targeted at power sensitive designs

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 2.5, May 2014 MachXO2 Family Data Sheet Introduction February 2014 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 2.6, July 2014 MachXO2 Family Data Sheet Introduction February 2014 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

LCMXO2-4000HC

Abstract: LCMX02 Lattice XO2 LCMXO2-4000 LCMX02 1200 wishbone HE 021 LCMX02-2000 CABGA 17 x 17 thermal resistance lcmxo2 7000he pcb layout
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 01.7, February 2012 MachXO2 Family Data Sheet Introduction February 2012 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

LCMX02

Abstract: LCMX02 1200 LCMXO2-1200HC-4TG144C LCMXO2-4000HC LCMXO2-1200HC-4MG132C lcmxo2-1200 TQFP-144 footprint LCMXO2-7000HC LCMXO2-640HC-4TG100C LCMX02-2000
Contextual Info: MachXO2 Family Data Sheet Preliminary DS1035 Version 01.5, August 2011 MachXO2 Family Data Sheet Introduction April 2011 Features Preliminary Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O 

LCMXO2-4000

Abstract: LCMX02 LCMX02 1200 MACHXO2 7000 pinout file LCMXO2 640HC LCMXO2-4000HC LCMXO2-1200HC-4TG100C LCMXO2-7000HC MachXO2 LCMXO2-1200HC-4MG132C
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 01.9, April 2012 MachXO2 Family Data Sheet Introduction March 2012 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.4, February 2014 MachXO2 Family Data Sheet Introduction February 2014 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

LCMXO2-256 pinout

Contextual Info: MachXO2 Family Data Sheet Preliminary DS1035 Version 01.2, April 2011 MachXO2 Family Data Sheet Introduction April 2011 Features Preliminary Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O 

a6252

Abstract: CS144 TQ100 TQ144 XC9500XV XC95144XV
Contextual Info: XC95144XV High-Performance CPLD R DS051 v2.2 August 27, 2001 1 Advance Product Specification Features Power Estimation • 144 macrocells with 3,200 usable gates • Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins)

LCMX02 1200

Abstract: LCMX02 LCMX02 256 LCMX02 640 MACHXO2 1200 pinout file LCMXO2-1200HC-4MG132C MACHXO2 7000 pinout file MACHXO2-1200ZE LCMXO2-7000 LCMXO2-2000
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 01.8, March 2012 MachXO2 Family Data Sheet Introduction March 2012 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only