TOE 35 INT Search Results

Siliconix mosfet smp4n60

Contextual Info: IC41C8512 IC41LV8512 Document Title 512K x 8 bit Dynamic RAM with EDO Page Mode Revision History Revision No History Draft Date Remark 0A Initial Draft September 28,2001 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

Contextual Info: IS41C8512 IS41LV8512 512K x 8 4-MBIT DYNAMIC RAM WITH EDO PAGE MODE DESCRIPTION The 1+51 IS41C8512 and IS41LV8512 is a 524,288 x 8-bit FEATURES • • • • Extended Data-Out (EDO) Page Mode access cycle TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1024 cycles /16 ms

IC41C1665-35K

Abstract: IC41C1665-35KI
Contextual Info: IC41C1665 IC41LV1665 Document Title 64K x16 bit Dynamic RAM with Fast Page Mode Revision History Revision No History Draft Date 0A Initial Draft October 17,2001 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

Contextual Info: IC41C16256 IC41LV16256 Document Title 256Kx16 bit Dynamic RAM with EDO Page Mode Revision History Revision No History Draft Date 0A 0B Initial Draft Revise for typo on page 20 August 9,2001 December 18,2001 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

Contextual Info: IC41SV4105 Document Title 1Mx4 bit Dynamic RAM with Fast Page Mode Revision History Revision No History Draft Date Remark 0A Initial Draft October 29,2001 Preliminary The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

t04 68 3 pin controller

Abstract: 5256VA 5384VA 5512VA CLK32
Contextual Info: ispLSI 5256VA In-System Programmable 3.3V SuperWIDE High Density PLD — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms

5256VA

Abstract: 5384VA 5512VA b09 n03
Contextual Info: ispLSI 5256VA In-System Programmable 3.3V SuperWIDE High Density PLD — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms

Contextual Info: INTERNATIONAL CMOS TECHNOLOGY, INC. PEEllM 153 CMOS Programmable Electrically Erasable Logic Device Features FPLA ARCHITECTURE — Programmable AND/OR arrays — 8 inputs and 10 l/Os — 42 product terms: 32 logic terms, 10 control terms — 10 sum terms • ADVANCED CMOS EEPROM TECHNOLOGY

Contextual Info: IC41UV4105 Document Title 1Mx4 bit Dynamic RAM with Fast Page Mode Revision History Revision No History Draft Date Remark 0A 0B Initial Draft 1.Change for VCC 2.6±0.3 to 2.6±0.2V August 9,2001 August 24,2001 Preliminary The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

A12B11

Abstract: d-t pt 5000VA 5256VA 5384VA 5512VA 5512VA-110LB388 208pin PQFP
Contextual Info: ispLSI 5512VA In-System Programmable 3.3V SuperWIDE High Density PLD — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms

IS41LV16256B

Abstract: 41LV16256B
Contextual Info: ISSI IS41LV16256B 256K x 16 4-MBIT DYNAMIC RAM WITH EDO PAGE MODE APRIL 2005 FEATURES DESCRIPTION • TTL compatible inputs and outputs • Refresh Interval: 512 cycles/8 ms • Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout

Contextual Info: INTERNATIONAL CMOS TECHNOLOGY, INC. PEEL173 CMOS Programmable Electrically Erasable Logic Device Features • FPLA ARCHITECTURE ■ ADVANCED CMOS EEPROM TECHNOLOGY — — — ■ LOW POWER CONSUMPTION — 35m A + 1 .OmA/MHz max ■ COMPATIBLE PERFORMANCE

AT49BV1024A

Abstract: AT49LV1024A
Contextual Info: Features • • • • • • • • • • • Single-voltage Operation Read/Write Operation: 2.7V to 3.6V BV . 3.0V to 3.6V(LV) Fast Read Access Time – 45 ns Internal Program Control and Timer 8K Word Boot Block with Lockout Fast Erase Cycle Time – 1.5 Seconds

Contextual Info: UTCAM-EngineTM Hardware Specification Nov. 1999 FEATURES External Memory q Addresses up to 32 gigabytes of memory q Can drive either SSRAM or SDRAM Host Interface q Configurable data bus Performance and Flexibility q Rapid association matching for exact match seeks

Contextual Info: Features • Single-voltage Operation • • • • • • • • • – 5V Read – 5V Reprogramming Fast Read Access Time – 35 ns Internal Program Control and Timer 8K Word Boot Block with Lockout Fast Erase Cycle Time – 10 seconds Word-by-word Programming – 10 µs/Word Typical

Contextual Info: Lattice ; ; ; ; Semiconductor •• ■■ Corporation ispLSr 5256VA VANTI S In-System Programmable 3.3V SuperWIDE High Density PLD Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore

Contextual Info: INTERNATIONAL CMOS TECHNOLOGY, INC. PEEL253 CMOS Programmable Electrically Erasable Logic Device Features • ADVANCED CMOS EEPROM TECHNOLOGY ■ FPLA ARCHITECTURE ■ COMPATIBLE PERFORMANCE — tpD = 30ns max, to E = 30ns max SUPERSET REPLACEMENT FOR PLS153

Contextual Info: & 27HC256 Microchip 256K 32K x 8 High Speed CMOS EPROM FEATURES DESCRIPTION • The Microchip Technology Inc 27HC256 is a CMOS 256K bit (electrically) Programmable Read Only Memory. The device is organized into 32K words of 8 bit each. Advanced CMOS technology allows bipolar speed with

atmel part for AT29C512

Abstract: AT29C512-90 AT29C512-12PC AT29C512-12pc datasheet AT29C512 AT29C512-12 AT29C512-15 AT29C512-70 AT29C512-70JC AT29C512-70PC
Contextual Info: AT29C512 Features • • • • • • • • • • • • Fast Read Access Time - 70 ns 5-Volt-Only Reprogramming Sector Program Operation Single Cycle Reprogram Erase and Program 512 Sectors (128 bytes/sector) Internal Address and Data Latches for 128-Bytes

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS05-11416-1E MEMORY Mobile FCRAMTM CMOS 16 Mbit 1 M word x 16 bit Mobile Phone Application Specific Memory MB82D01171B-60L/-60LL/-70L/-70LL CMOS 1,048,576-WORD × 16 BIT Fast Cycle Random Access Memory with Low Power SRAM Interface

5652

Abstract: transistor k81
Contextual Info: IC41C16105 IC41LV16105 1M x 16 16-MBIT DYNAMIC RAM WITH FAST PAGE MODE DESCRIPTION The 1+51 IC41C16105 and IC41LV16105 are 1,048,576 x FEATURES • TTL compatible inputs and outputs; tristate I/O • Refresh Interval: 1,024 cycles/16 ms • Refresh Mode: RAS-Only, CAS-before-RAS (CBR),

MS16M0-XX

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4616112-X 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD4616112-X is a high speed, low power, 16,777,216 bits 1,048,576 words by 16 bits CMOS mobile

DM 0565

Abstract: transistor a6f
Contextual Info: IC41C82002 IC41LV82002 2M x 8 16-MBIT DYNAMIC RAM WITH EDO PAGE MODE FEATURES DESCRIPTION • Extended Data-Out (EDO) Page Mode access cycle • TTL compatible inputs and outputs • Refresh Interval: - 2,048 cycles/32 ms The 1+51 82002 Series is a 2,097,152 x 8-bit high-performance

SN54LVT8980A

Abstract: SN74LVT8980A SN74LVT8980ADW SN74LVT8980ADWR SNJ54LVT8980AFK SNJ54LVT8980AJT SNJ54LVT8980AW
Contextual Info: SN54LVT8980A, SN74LVT8980A EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES SCBS755A – APRIL 2002 – REVISED JULY 2002 D D D D D D D D D D SN54LVT8980A . . . JT PACKAGE SN74LVT8980A . . . DW PACKAGE (TOP VIEW)