TMS 3534 Search Results

Contextual Info: CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■

3M Touch Systems

Contextual Info: CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■

3M Touch Systems

Contextual Info: CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■

CY7C1371DV33

Contextual Info: CY7C1371DV33 18-Mbit 512 K x 36 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles

Contextual Info: CY7C1371DV33 18-Mbit 512 K x 36 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles

Contextual Info: CY7C1447AV25 36-Mbit 512 K x 72 Flow-Through SRAM 36-Mbit (512 K × 72) Flow-Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 512 K × 72 common I/O ■ 2.5 V core power supply ■ 2.5 V and 1.8 V I/O power supply ■

Contextual Info: CY7C1441AV25 CY7C1447AV25 36-Mbit 1 M x 36/512 K × 72 Flow-Through SRAM 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 1 M × 36/512 K × 72 common I/O ■ 2.5 V core power supply

Contextual Info: CY7C1441AV25 CY7C1447AV25 36-Mbit 1 M x 36/512 K × 72 Flow-Through SRAM 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM Functional Description Features • Supports 133 MHz bus operations ■ 1 M × 36/512 K × 72 common I/O ■ 2.5 V core power supply

Contextual Info: CY7C1441AV25 CY7C1447AV25 36-Mbit 1 M x 36/512 K × 72 Flow-Through SRAM 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 1 M × 36/512 K × 72 common I/O ■ 2.5 V core power supply

fx3 pin map

Abstract: CYUSB301X
Contextual Info: CYUSB301X, CYUSB201X EZ-USB FX3: SuperSpeed USB Controller Features • ■ ■ ■ ■ Universal serial bus USB integration ❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification 1.0 ❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0 ❐ High-speed On-The-Go (HS-OTG) host and peripheral

Pentium A80501-60

Contextual Info: in te i PENTIUM PROCESSOR Max. Operating Frequency 75 MHz 90 MHz 100 MHz 120 MHz 133 MHz 150 MHz 166 MHz 200 MHz 67 81 90 100 111 114 127 142 iCOMP* Index 2.0 Rating Note: Contact Intel Corporation for more information about iCOMP*lndex 2.0 ratings. Compatible with Large Software Base

TMS5220

Abstract: tms50c42 TMS50C20 SDS HB1 tms50c4 50C20 654P74 SINE VAWE crystal oscillator SPEECH CIRCUITS 654P64
Contextual Info: TMS50C20: A CMOS SPEECH SYNTHESIZER TMS50C20: A CMOS SPEECH SYNTHESIZER ♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦ USER'S MANUAL ♦♦♦♦♦♦♦♦♦♦♦♦♦ SEPTEMBER 1988 ♦♦♦♦♦♦♦♦♦♦♦♦♦♦

BGA FX3_121

Abstract: CYUSB301X CLKIN32 CYUSB3014-FBXIT WLCSP chip attach 131-BA gpio to i2C CYUSB3011 CYUSB3014-BZXC FX3_121
Contextual Info: CYUSB301X EZ-USB FX3: SuperSpeed USB Controller Features • ■ ■ ■ ■ Universal serial bus USB integration ❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification 1.0 ❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0 ❐ High-speed On-The-Go (HS-OTG) host and peripheral

CYUSB301X

Contextual Info: CYUSB301X EZ-USB FX3: SuperSpeed USB Controller Features • ■ ■ ■ ■ Universal serial bus USB integration ❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification 1.0 ❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0 ❐ High-speed On-The-Go (HS-OTG) host and peripheral

CYUSB301X

Contextual Info: CYUSB301X EZ-USB FX3 SuperSpeed USB Controller Features • Independent power domains for core and I/O ❐ Core operation at 1.2 V 2 ❐ I S, UART, and SPI operation at 1.8 to 3.3 V 2 ❐ I C operation at 1.2 V ■ 10- x 10-mm, 0.8-mm pitch Pb-free ball grid array BGA

A2F500 pin details

Abstract: A2F500 A2F060 A2F200 A2F200-fg256 IO05PDB0V0
Contextual Info: Revision 8 SmartFusion Customizable System-on-Chip cSoC Microcontroller Subsystem (MSS) • • • • • • • • • • • • Hard 100 MHz 32-Bit ARM Cortex -M3 – 1.25 DMIPS/MHz Throughput from Zero Wait State Memory – Memory Protection Unit (MPU)

Contextual Info: CS5376A Low-power, Multi-channel Decimation Filter Features Description 1- to 4-channel Digital Decimation Filter The CS5376A is a multi-function digital filter utilizing a low-power signal processing architecture to achieve efficient filtering for up to four ∆Σ modulators. By

TMS 3834

Abstract: geophone detector Atmel H122 sps H113 931 h68 sps 1951 atmel h118 atmel H116
Contextual Info: CS5376A Low Power Multi-Channel Decimation Filter Features Description 1 to 4 Channel Digital Decimation Filter The CS5376A is a multi-function digital filter utilizing a low-power signal processing architecture to achieve efficient filtering for up to four ∆Σ modulators. By combining

TMS 3834

Abstract: BRC 1310 SCR FIR 3 D DS6-12F 02 01 96 1101 40298 atmel 718 h107 d1 SCR ty 8016 CS4373A
Contextual Info: CS5376A Low-power, Multi-channel Decimation Filter Features Description z 1- to 4-channel Digital Decimation Filter ΠMultiple On-chip FIR and IIR Coefficient Sets ΠProgrammable Coefficients for Custom Filters ΠSynchronous Operation The CS5376A is a multi-function digital filter utilizing a

TMS 3834

Abstract: 40298 DS6-12F digital filter sinc filter CS4373 CS5376 CS5376A CS5376A-IQ geophone detector
Contextual Info: CS5376A Low Power Multi-Channel Decimation Filter Features Description 1 to 4 Channel Digital Decimation Filter Multiple On-Chip FIR and IIR Coefficient Sets Programmable Coefficients for Custom Filters Synchronous Operation Selectable Output Word Rate 4000, 2000, 1000, 500, 333, 250 SPS

atmel H116

Abstract: TMS 3834 40298 logic H113 BRC 1310 H123 H124 CS4373A CS5376 CS5376A
Contextual Info: CS5376A Low-power, Multi-channel Decimation Filter Features Description z 1- to 4-channel Digital Decimation Filter ΠMultiple On-chip FIR and IIR Coefficient Sets ΠProgrammable Coefficients for Custom Filters ΠSynchronous Operation The CS5376A is a multi-function digital filter utilizing a

A2F060

Contextual Info: Revision 10 SmartFusion Customizable System-on-Chip cSoC Microcontroller Subsystem (MSS) • • • • • • • • • • • • Hard 100 MHz 32-Bit ARM Cortex -M3 – 1.25 DMIPS/MHz Throughput from Zero Wait State Memory – Memory Protection Unit (MPU)

A2F500M3

Abstract: A2F500 A2F500 FG484 A2F200-FG484 A2F500 pin details A2F060 A2F060M A2F200M3 A2F200M3F-FG256 A2F200M3F
Contextual Info: Revision 9 SmartFusion Customizable System-on-Chip cSoC Microcontroller Subsystem (MSS) • • • • • • • • • • • • Hard 100 MHz 32-Bit ARM Cortex -M3 – 1.25 DMIPS/MHz Throughput from Zero Wait State Memory – Memory Protection Unit (MPU)

Contextual Info: pMC-Sierra, Inc. PM7323 RCMP-200 P r e l im in a r y I n f o r m a t io n is su e 1 ROUTING CONTROL, MONITORING AND POUCING 200 Mbps FEA TU R ES • Monolithic single chip device which handles ATM switch Ingress VPI/VCI address translation, cell appending, cell rate policing, counting, and OAM requirements