TMS 320 C 6X PROCESSOR DATASHEET Search Results

PC755BM8

Abstract: MCP 67 MV PC745 PC755M8 PCX755B
Contextual Info: Features • • • • • • PC755BM8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz Maximum L2 Cache Frequency = 175 MHz Maximum 60x Bus Frequency = 66 MHz

PC745

Abstract: PC755M8 PCX755B
Contextual Info: Features • • • • • • PC755M8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz Maximum L2 Cache Frequency = 175 MHz Maximum 60x Bus Frequency = 66 MHz

TMS 320 C 6X processor

Abstract: 2164A PC745 PC755M8 2164A dynamic ram cop interface l2-dp
Contextual Info: Features • • • • • • PC755M8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 300 MHz Maximum L2 Cache Frequency = 150 MHz Maximum 60x Bus Frequency = 66 MHz

cop interface

Abstract: PC745 PC755M8 PLL VCO MIL-PRF-38535 X755M
Contextual Info: Features • • • • • • PC755M8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz Maximum L2 Cache Frequency = 175 MHz Maximum 60x Bus Frequency = 66 MHz

TSPC603R

Abstract: microprocessor LNM80 DH21
Contextual Info: TSPC603R PowerPC 603e RISC Microprocessor Family PID7t-603e Datasheet Features • • • • • • • Superscalar 3 Instructions per Clock Peak Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support

Atmel - SAM3N ARM Cortex M3 Microcontroller

Abstract: Cortex A9 instruction set EEFC AT91SAM AT91SAM7S ISO7816 LQFP100 LQFP48 LQFP64 0x400E0A00
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 48 MHz – Thumb®-2 instruction – 24-bit SysTick Counter – Nested Vector Interrupt Controller Pin-to-pin compatible with AT91SAM7S legacy products 48- and 64-pin versions and

microprocessor

Abstract: G172
Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

0828H

Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

BERG CONNECTOR

Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

SAM3N

Abstract: swdio timing Atmel - SAM3N ARM Cortex M3 Microcontroller Cortex A9 instruction set 431 regulator PA20 cortex a5 SAM3N00A ATSAM3N0BA-MU 0x400E1000
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 48 MHz – Thumb®-2 instruction – 24-bit SysTick Counter – Nested Vector Interrupt Controller Pin-to-pin compatible with SAM7S legacy products 48- and 64-pin versions and

cortex a9

Abstract: ARM Cortex A8 arm cortex a9 cortex a9 core cortex a9 qfp Cortex A15 cortex a9 core processor architecture atmel SAM3S ATSAM3S2B cortex a15 core
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) Memories

atmel SAM3S

Abstract: SAM3S4B sam3s bootloader atsam3s4a 6500DS
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S series (48- and 64-pin versions) Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

SM320VC33

Contextual Info: SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 D High-Performance Floating-Point Digital D Signal Processor DSP : - SM/SMJ320VC33-150 - 13-ns Instruction Cycle Time - 150 Million Floating-Point Operations Per Second (MFLOPS)

ATSAM3S2B

Abstract: SAM3S sam3s bootloader atsam3s4a ATSAM3S4 ATSAM3S Cortex A9 instruction set cortex a15 core sam3s4c ATSAM3S4BA-AU
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) Memories

Mips 34k

Abstract: SM320VC33
Contextual Info: SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 D High-Performance Floating-Point Digital D Signal Processor DSP : - SM/SMJ320VC33-150 - 13-ns Instruction Cycle Time - 150 Million Floating-Point Operations Per Second (MFLOPS)

s23670w002

Abstract: DD 127 D TRANSISTOR cga motorola PC750A IN 750a t5 CBGA360 TSPC740A TSPC750A CI-CBGA360
Contextual Info: Features • • • • • • • • • • • • • • • 12.4 SPECint95, 8.4 SPECfp95 at 266 MHz TSPC750A with 1 MB L2 at 133 MHz 11.5 SPECint95, 6.9 SPECfp95 at 266 MHz (TSPC740A) 488 MIPS at 266 MHz Selectable Bus Clock (11 CPU Bus Dividers up to 8x)

MPC750

Contextual Info: Features • • • • • • • • • • • • • • • 12.4 SPECint95, 8.4 SPECfp95 @ 266 MHz TSPC750A with 1 MB L2 @ 133 MHz 11.5 SPECint95, 6.9 SPECfp95 @ 266 MHz (TSPC740A) 488 MIPS @ 266 MHz Selectable Bus Clock (11 CPU Bus Dividers up to 8x)

0.18-um CMOS technology length and width

Abstract: SMJ320VC33HFGM150 J4 diode SM320VC33
Contextual Info: SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034C – FEBRUARY 2001 – REVISED NOVEMBER 2001 D High-Performance Floating-Point Digital D D D D D D D D D D D Signal Processor DSP : – SM/SMJ320VC33-150 – 13-ns Instruction Cycle Time – 150 Million Floating-Point Operations

thumb instructions for stepper motor interfacing

Abstract: Cortex A9 instruction set ATSAM3S8BA-MU 0x28AB0A60 11090AS cortex a15 core QFN64 9x9 ATmel cortex a9 microcontroller ARM cortex a15 cpu sdhc sam
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (64-pin versions), SAM3S4/2/1 products

Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (64-pin versions), SAM3S4/2/1 products

tl7705

Abstract: SM320VC33
Contextual Info: SM320VC33−EP DIGITAL SIGNAL PROCESSOR SGUS037C - AUGUST 2002 - REVISED JANUARY 2003 D Controlled Baseline D D D D D D D D D D D † - One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of -40 °C to 100°C A Suffix , and -55 °C to 125°C (M Suffix)

cga motorola

Abstract: CBGA360 MPC7400 PC745 PC755 N-19 CI-CGA360 PowerPC755
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

hall sensor u18 032

Abstract: CBGA360 MPC7400 PC745B PC755B CBGA-255 atmel 0820 PowerPC755B
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755B 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745B) 733 MIPS at 400 MHz (PC755B) at 641 MIPS at 350 MHz (PC745B) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)