TMS 300 Search Results

intel 2101

Abstract: TMS4039 40392 22-PIN TMS403 TMS4039JL
Contextual Info: TMS 4039 Jl, Nl; TMS 4039-1 Jl, Nl; TMS 4039-2 Jl, Nl 256-WORD BY 4-BIT STATIC RANDOM-ACCESS MEMORIES MOS lSI BULLETIN • • 256 x 4 Organization Static Operation {No Clocks, No Refresh} • 3 Performance Ranges: ACCESS TIME MAX TMS 4039 TMS 4039-1 TMS 4039-2

EI-30

Abstract: EI - 33 EI -40C
Contextual Info: TMS Vishay Aztronic Mains Transformers FEATURES • Potted in a case to be mounted on a PCB • Potting gives a high isolation and good aging • Pins are on a standard 5mm pitch DIMENSIONS in millimeters TMS 0.5 / 1 / 1.2 / 1.8 / 2.5 TMS 5 TMS 3.2 32 44.1

SN7400

Abstract: SN7416 SN7426
Contextual Info: MOS LSI TMS 3000 L R -DUAL 25-BIT STATIC SHIFT REGISTER TMS 3001 LR-DUAL 32-BIT STATIC SHIFT REGISTER featu es Static logic DC to 1 MHz operation Low power dissipation Push-pull output buffers TTL compatible description The TMS 3000 LR and TMS 3001 LR are dual static shift registers. Each device contains tw o dc-to-1-MHz shift regis­

TIL-220

Abstract: TMS1121 TIL220 TIL322 LED TIL220
Contextual Info: 1. TMS 1121 UNIVERSAL TIMER CONTROLLER INTRODUCTION The TMS 1121 Universal Tim er C ontroller is a mask-programmed version o f the TMS 1000 Fam ily 4 -b it single chip m icrocom puter providing the fu n ctio n o f a programmable tim e o f day, day o f week co ntroller. When the TMS 1121 is

2532 eprom

Abstract: 25l32 eprom 2532 MA 25L32 tms 2532 jl 2532 2532 eprom texas TMS2532 2532 rom TMS4732
Contextual Info: MOS LSI TMS 2532-30 JL, TMS 2532-35 JL, TMS 2532-45 JL. TMS 25L32-45 JL 32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES • Organization . . . 4 0 9 6 X 8 • Single + 5 V Power Supply • Pin Compatible with Existing R O M s and E P R O M s 8K, 16K, 32K, and 64K

CD 4050 pin diagram

Abstract: TMS4050 40501 TMS 4050 NL 18-PIN 1975-REVISED ot220
Contextual Info: MOS LSI TMS 4050 Jl, Nl; TMS 4050-1 Jl, Nl; TMS 4050-2 Jl, Nl 4096-81T DYNAMIC RANDOM-ACCESS MEMORIES BULLETIN NO. DL-S 7512242, FEBRUARY 1975-REVISED MAY 1975 • • • • 4096 x 1 Organization 18-Pin 300-Mil Package Configuration Multiplexed Data Input/Output

TMS4036-2

Abstract: 40361 40362 tms4036 4036 20-PIN TMS403
Contextual Info: TMS 4036 Jl, Nl; TMS 4036-1 Jl, Nl; TMS 4036-2 Jl, Nl 64-WORD BY 8-BIT STATIC RANDOM-ACCESS MEMORIES MOS lSI BULLETIN NO. DL-S 7512277, MAY 1975 • o 64 x 8 Organization Static Operation No Clocks, No Refresh o Compact 20-Pin 300-Mil Dual-in-Line Package

TMS6009

Abstract: TTL counter SN5442 MOS ANALOG SWITCHES
Contextual Info: MOS LSI TMS 6005 J R , NC; TMS 6009 JR , NC SIX-CHANNEL ANALOG SWITCHES D ESIGN ED FOR HIGH-SPEED M U LTIPLEXIN G APPLICATIONS • Dual-in-line package • rDS on •• ■200 Q. max description The TMS 6005 JR/NC and TMS 6009 JR/NC ana­ TOP VIEW log switches are P-channel enhancement-mode MOS

TMS4030

Abstract: 40301 ci 4030 22-PIN TMS403 TMS4030JL TMS 4030
Contextual Info: MOS LSI TMS 4030 JL, NL; TMS 4030-1 JL, NL; TMS 4030-2. JL, NL 4096-81T DYNAMIC RANDOM-ACCESS MEMORIES BULLETIN NO. DL-S 7512240, FEBRUARY 1975 22-PIN CERAMIC AND PLASTIC DUAL•IN-LiNE PACKAGES TOP VIEW • 4096 x 1 Organization • 3 Performance Ranges:

TMS4060

Abstract: RD4000 TMS 250 TMS4060-1 TMS4060-2 4060 PIN DIAGRAM 40601 40602
Contextual Info: MOS LSI TMS 4060 JL, NL; TMS 4060-1 JL, NL; TMS 4060-2 JL, NL 4096-BIT DYNAMIC RANDOM-ACCESS MEMORIES BULLETIN NO. DL•S 7512241, FEBRUARY 1975 22·PIN CERAMIC AND PLASTIC DUAL-IN-L1NE PACKAGES TOP VIEW • 4096 x 1 Organization • 3 Performance Ranges:

intel 2112

Abstract: c mos 4043 40431 TMS4043 40432 74 ttl
Contextual Info: MOS LSI TMS 4043 JL, NL; TMS 4043-1 JL, NL; TMS 4043-2 JL, NL 256-WORD BY 4-BIT STATIC RANDOM-ACCESS MEMORIES BULLETIN • 256 x 4 Organization • • • Common I/O 16-Pin Package Static Operation No Clocks, No Refresh 3 Performance Ranges: • TMS4043

TMS4042

Abstract: TMS4042-2 intel 2111 4042 PIN DIAGRAM Tms 1000 4042 BE 40422 18-PIN EE 4042 TMS4042/2111NL
Contextual Info: TMS 4042 JL. NL; TMS 4042-1 JL. NL; TMS 4042-2 JL, NL 256-WORD BY 4-BIT STATIC RANDOM-ACCESS MEMORIES MOS LSI BULLETIN • • • • • 256 x 4 Organization Common I/O 18-Pin Package Static Operation No Clocks, No Refresh 3 Performance Ranges: ACCESS

TMS4063

Abstract: ql 5012 SN75370 22-PIN AD-2000
Contextual Info: TMS 4062 JL, NL; TMS 4063 JL, NL 1024-WORD BY l-BIT DYNAMIC RANDOM-ACCESS MEMORIES MOS LSI BULLETIN • 1024 x 1 Organization • Access Time . 130 ns Maximum • Cycle Time . 200 ns Maximum • Low Power Dissipation: NO. DL-S 7512272. MAY 1975 TMS 4062 JL, NL

RW-2513

Abstract: B033B SAE-AS81531 HS032WE2NF038B HX-SCE BTM 640 RPS heat-shrinkable sleeves AM6310 Transparent, Extended ribbon cable 8 x 8 DOT MATRIX 32mm
Contextual Info: Wire and Harness ID Products Heat Shrink/Cable Markers TMS-SCE Military grade heat shrinkable wire identification sleeves TMS-SCE marker sleeves are designed to meet the wire and cable marking needs of manufacturers with high performance requirements. Made from durable, flame retarded, radiationcrosslinked heat-shrinkable polyolefin, TMS-SCE marker sleeves

intel 2102 Static RAM

Abstract: TMS4035 2102 Static RAM TMS4034 power must office 650 TMS4033 2102-2 RAM TMS403 TMS4030 TMS4035JL
Contextual Info: MOS LSI TMS 4033 JL, NL; TMS 4034 JL, NL; TMS 4035 JL, NL 1024-WORD BY 1-81T STATIC RANDOM-ACCESS MEMORIES BULLETIN NO. DL-S 7512189, OCTOBER 1974-REVISED MAY 1975 • 1024 x 1-Bit Organization • Static Operation No Clocks, 16-PIN CERAMIC AND PLASTIC DUAL-IN-LiNE PACKAGES

tms 3

Contextual Info: MOS LSI TMS 3112 JC, NC; TMS 3122 JC, NC; TMS 3123 JC, NC HEX 32-81T STATIC SHIFT REGISTERS BULLETIN NO. DL-S 7512261, MAY 1975 • • • • • • • • • DC to 2-MHz Operation Static Configuration Single TTL-Compatible Clock Inputs and Outputs are Fully

TMS1121

Abstract: IN645 cook timer TMS1121NLL 1121 LED 7 day timer controller day and night switch q2t2222 traffic light controller week display circuit
Contextual Info: 1. TMS 1121 U N IVERSAL TIM E R CO NTRO LLER INTRO DUC TIO N The TMS 1121 Universal Tim er C ontroller is a mask-programmed version o f the TMS 1000 Fam ily 4 -b it single chip m icrocom puter providing the fu n ctio n o f a programmable tim e o f day, day o f week co n tro lle r. When the TMS 1121 is

ci 4030

Abstract: ci 4060 4060 PIN DIAGRAM TMS 4030 TMS4030 TMS4060 a5 chip 4060 18-PIN 22-PIN
Contextual Info: TMS 4030 JR, TMS 4050 JR, TMS 4060 JR SMC 4030 JR, SMC 4050 JR, SMC 4060 JR 4096-81T RANDOM-ACCESS MEMORIES MOS LSI BULLETIN NO DL-S 7512276, MAY 1975 EXTENDED TEMPERATURE RANGE AND HI-REL DEVICES • 4096 x 1 Organization • Extended Temperature Range _55° C to 85° C

CI 4069

Abstract: 4060 PIN DIAGRAM LM 4069 ACT 4060 ACT 4060 A ci 4060 4060 RAM TMS4060 4069 14 pin ct 4060
Contextual Info: TMS 4060 JL. NI 4096-BIT DYNAMIC RANDOM-ACCESS MEMORIES MOS LSI 2 2 -P IN C E R A M IC A N O P L A S T IC D U A L - IN L IN E P A C K A G E S TO P V IE W 40 9 6 x 1 O rganization 3 Perform ance Ranges: ACCESS TIME (M A X I TMS 4 0 6 0 TMS 4 06 0-1 TMS 4 0 6 0 -2

4051 16 PIN DIAGRAM

Abstract: 40511 4051 pin diagram 4051 timing diagram 18-PIN TMS4051
Contextual Info: MOS LSI TMS 4051 JL, NL; TMS 4051-1 JL, NL 4096-81T DYNAMIC RANDOM-ACCESS MEMORIES BULLETIN NO. DL•S 7512256, MAY 1975 • • • • • • • • • • 4096 x 1 Organization 18-Pin 300-Mil Package Configuration Single Low-Capacitance TTL-Compatible Clock

tms 2000

Abstract: TMS2100 TMS-2000 TMS 2100 TMS2000 TMS 2200
Contextual Info: TMS 2000 JC , NC; TMS 2200 JC. NC PROGRAMMABLE LOGIC ARRAYS MOS LSI features Low-threshold MOS/bipolar technology Static operation Push-pull or single-ended output buffers Optional internal MOS pull-up resistor on inputs T T L compatible CD IP or plastic package

Contextual Info: MOS LSI TMS 3120 JC, NC; TMS 3121 JC, NC QUADRUPLE 80-, 64-BIT STATIC SHIFT REGISTERS BULLETIN • DC to 2.5-MHz Operation • Static Configuration • Single TTL-Compatible Clock • Inputs and Outputs Fully TTL-Compatible • Push-Pull Output Buffers •

27L08-45

Abstract: 2708 eprom 27L08 2708-45 74LS TTL 245 TMS 2708 JL a1023 ansi y32.14 diagram 2708 memory TMS2708
Contextual Info: TMS 2708-35 JL. TMS 2708-45 JL, TMS 27L08-45 JL 1024-WORD BY 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES MOS LSI D E C E M B E R 1 9 7 9 - R E V I S E D M A Y 1982 1024 X 8 Organization A ll Inputs and O utputs F ully T T L Compatible 24-PIN CER P AK D U A L -IN -L IN E PACKAG E

Contextual Info: MOS LSI TMS 3112 JC, NC; TMS 3122 JC, NC; TMS 3123 JC. NC HEX 32-BIT STATIC SHIFT REGISTERS B U L L E T I N NO. DL-S 7 5 1 2 2 6 1 , M A Y 1 9 7 5 • DC to 2 -M H z Operation • Static Configuration • Single T TL -C o m p atib le Clock TM S 3112 • Inputs and Outputs are Fully