TMS 0119 Search Results

4A256

Abstract: MACH4A I1017 4a32
Contextual Info: ADVANCE INFORMATION VANTI S BEYO N D PERFO RM ANCE MACH 4A CPLD Family High Performance EE CMOS Programmable Logic With Maximum Ease Of Use DISTINCTIVE CHARACTERISTICS Features ♦ High-performance, EE CMOS 3.3-V CPLD Family ♦ Flexible architecture for rapid logic designs

Contextual Info: MACH 5 CPLD Family BEY O N D PER FO RM AN C E F ifth G e n e r a t i o n M A C H A r c h i t e l i . . ^ FEATURES P u b lic atio n # 2 0 4 4 6 A m e n d m e n t/0 Rev: G Issu e D ate: N o v e m b e r 1 9 9 8 MACH Families ♦ High logic densities and l/Os for increased logic integration

Contextual Info: MACH 5 CPLD Family BEYOND PERFORMANCE Fifth G eneration MACH A r c h it e l i. . ^ FEATURES — 128 to 512 m acrocell densities — 68 to 256 l/Os ♦ Wide selection of density and I/O combinations to support most application needs — 6 m acrocell density o ptions

CXO 049

Abstract: GX6101 CXO 043 BX61 CI043 CXO 046 ci pal 014 V/ci pal 014
Contextual Info: MACH 4 CPLD Family BEYOND PERFO R M A N CE High Performance EE CMOS Programmable Logic FEATURES ♦ High-performance, EE CMOS 3.3-V & 5-V CPLD families ♦ Flexible architecture for rapid logic designs — Excellent First-Tim e-Fit and refit feature — SpeedLocking™ performance for guaranteed fixed timing

MUX2T01

Contextual Info: MACH 5 CPLD Family BE Y O N D PE R FO RM AN C E Fifth G eneration MACH A rc h it^ w ^ .^ FEATURES P u b lic atio n # 2 0 4 4 6 A m en d m en t/O Rev: G Issu e D ate: N o v e m b e r 1 9 9 8 MACH Families ♦ High logic densities and l/Os for increased logic integration

1 - bit full adder multisim

Abstract: MACH4A
Contextual Info: MACH 4A Family BEYO N D PERFO RM A N CE High Performance EE CMOS Programmable Logic With Maximum Ease Of Use DISTINCTIVE CHARACTERISTICS Unique Features ♦ High-performance, EE CMOS 3.3-V CPLD Family ♦ First-Time-Fit and Good Refit ♦ High Speed — 5.5ns t PD Commercial and 7.5ns t PD Industrial

KJ00

Contextual Info: MACH 4 CPLD Family BEYOND PERFORM ANCE High Performance EE CMOS Programmable Logic FEATURES ♦ High-performance, EE CMOS 3.3-V & 5-V CPLD families ♦ Flexible architecture for rapid logic designs ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ — Excellent First-Time-Fit and re fit

393 EZ 952

Abstract: 5K432 m4as 12864j n1085 049G1 Programming mach 130
Contextual Info: D "V High Performance EE CMOS Programmable Logic FEATURES ♦ High-performance, EE CMOS 3.3-V & 5-V CPLD families ♦ Flexible architecture for rapid logic designs — Excellent First-Time-Fit and refit — SpeedLocking™ for guaranteed fixed timing — Central, input and output switch matrices for 100% routability and 100% pin-out retention

12f s091

Abstract: T1B10 pdcr 900 "XS 101" ocr6 tlcs90 8e s085 eeprom s130 RC1B S091
Contextual Info: TO SH IBA UNDER DEVELOPMENT TMP95CW86/TMP95FW86 CMOS 16-Bit Microcontroller TMP95CW86F / TMP95FW86F TMP95CW86DF / TMP95FW86DF 1. Outline and Features The TMP95CW86 and TMP95FW86 are high-speed, high-perform ance 16-bit microcontrollers developed for medium- to large-scale control applications.

Contextual Info: Lattice is ;Semiconductor I Corporation L S I3 1 6 0 High Density Programmable Logic Features • HIGH-DENSITY PROGRAMMABLE LOGIC — 160 I/O Pins — 7000 PLD Gates — 320 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: FINAL COM'L: -7 /1 0 /1 2 /1 5 IN D :-1 0 /1 2 /1 5 /2 0 M A C H 5 -1 9 2 V A N T I S COMP ANY MACH5-192/68-7/ 10/ 12/15 M ACH5-192/104-7/ 10/ 12/15 MACH5-192/ 120-7/10/12/1 5 M ACH5-192/160-7/ 10/ 12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS

Contextual Info: Lattica ! Semiconductor ICorporation ispLSI 5384V In-System Programmable SuperWlde High Density PLD ispDS+™ HDL Synthesis-Optimized Logic Fitter — Supports Leading Third-Party Design Environments for Schematic Capture, Synthesis and Timing Simulation

tms 0119

Contextual Info: Lattice ispLSr 3192 ;Semiconductor I Corporation High Density Programmable Logic Features IH B • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: Specifications ispLSI andpLSI 3192 üiLattice ispLSI and pLSI 3192 • " ■■" Semiconductor ■■■■■■ Corporation High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates

Contextual Info: FINAL COM'L: -7/10/12/15 IND:-10/12/15/20 M A C H 5-192 V A N A IM T A M D I S C O M P A N Y MACH5-192/68-7/10/12/15 MACH5-192/120-7/10/12/15 M ACH5-192/104-7/10/12/15 M ACH5-192/160-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS

Contextual Info: Xgjf PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

MACH5 from amd

Contextual Info: COM’L: -7/10/12/15 PRELIMINARY AMD£I IND: -10/12/15/20 The MACH5-192 MACH5-192/68-7/10/12/15/20 MACH5-192/104-7/10/12/15/20 MACH5-192/120-7/10/12/15/20 MACH5-192/1 60-7/10/12/15/20 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS • Fifth generation MACH architecture

NCL025

Contextual Info: •■■■■■■\fct>cw.-. s a s iâ s ^ 5^” .w s & v PRELIMINARY _ . "T U ltra 3 7 5 1 2 UltraLogic 512-Macrocell ISR™ CPLD Features • • • • • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

Contextual Info: P R ELIM IN A R Y BEYOND PERFORMANCE C O M 'L : -5 /7 /1 0 /1 2 I N D : -7 /1 0 /1 2 /1 5 M A C H 5 LV -256 MACH5LV-256/68-5/7/10/12 MACH5LV-256/120-5/7/1 0/12 MACH5LV-256/104-5/7/10/12 MACH5 n/160-5/7/10/12 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS

MPC5634M

Abstract: bosch Knock sensor MAPBGA208 BOSCH 001 107 408 LQFP-144 footprint VRC33 Nexus S JTAG pins automotive sensors bosch LQFP 144 footprint mpc5554 emios
Contextual Info: Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5634M Rev. 3, 2/2009 MPC5634M MPC5634M Microcontroller Data Sheet • Operating Parameters – Fully static operation, 0 MHz - 80 MHz plus 2% frequency modulation - 82 MHz – -40 °C to 150 °C junction temperature operating range

rj48_con

Abstract: 5B1 package SMD 11D4 pc motherboard schematics 11B7 5A6 t smd
Contextual Info: DS21352DK T1 Single-Chip Transceiver Design Kit Daughter Card www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21352 design kit is an easy-to-use evaluation board for the DS21352 T1 single-chip transceiver SCT . The DS21352DK is intended to be used as a

5A6 smd

Abstract: 10uF 160v Transistor 8c4 6c2 diode 9A4 SMD SMD 6c6 TANTALUM SMD CAPACITOR CROSS-REFERENCES Transistor 6C5 DK101 DK2000
Contextual Info: DS21354DK E1 Single-Chip Transceiver Design Kit Daughter Card www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21354 design kit is an easy-to-use evaluation board for the DS21354 E1 single-chip transceiver SCT . The DS21354DK is intended to be used as a

5A6 smd

Abstract: 4C6 SPECIFICATIONS 11d4 Transistor 8c4 smd 8c7 5a7 02 11d5 XC95144XL-10TQ100c DK101 DS18
Contextual Info: DS21352DK T1 Single-Chip Transceiver Design Kit Daughter Card www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21352 design kit is an easy-to-use evaluation board for the DS21352 T1 single-chip transceiver SCT . The DS21352DK is intended to be used as a

SAA4991WP

Abstract: sMD .v05 smd V05 p14 115 SAA4979H itu 656 output converter smd 01c1 80C51 QFP128 SAA4992H
Contextual Info: INTEGRATED CIRCUITS DATA SHEET SAA4979H Sample rate converter with embedded high quality dynamic noise reduction and expansion port Product specification 2002 May 28 Philips Semiconductors Product specification Sample rate converter with embedded high quality