TMP82 Search Results

P8251A

Abstract: P82C51A tmp8251 82C51A P8251
Contextual Info: T O S H IB A TM P82C51A TMP82C51AP-2 /TMP82C51AP-10 TMP82C51 AM-2/TMP82C51 AM-10 PROGRAM M ABLE COMMUNICATION INTERFACE 1. GENERAL DESCRIPTION T he TM P82C51A is th e in d u stry sta n d a rd U n iv ersa l S ynchron o u s/A sy n ch ro n o u s R eceiver/T ransm itter USART th a t is fabricated u sin g C-MOS silicon g a te technology.

P8279

Abstract: 8279-5
Contextual Info: TOSHIBA TMP8279 PRO GRAM M ABLE KEYBOARD/DISPLAY INTERFACE TMP8279P-5 1. GENERAL DESCRIPTION T h e T M P 8 2 7 9 P -5 h e r e i n a f t e r r e f e r r e d to a s T M P 8 2 7 9 is a p r o g r a m m a b le k e y b o a rd /d isp la y in te rfa c e d e sig n e d for u se as th e T L C S -85 A m ic ro c o m p u te r p e rip h e ra l.

TMP8237

Contextual Info: T O S H IB A TMP82C37A MULTIMODE DMA CONTROLLER TMP82C37AP-5/TMP82C37AM-5/TMP82C37AT-5 1. GENERAL DESCRIPTION T h e T M P 8 2 C 3 7 A P -5 /A M -5 /A T -5 h e r e in a f t e r r e f e r r e d to a s T M P 8 2 C 3 7 A is a m u ltim o d e d ire c t m e m o ry access (DM A) c o n tro lle r.

MPU85-347

Contextual Info: TOSHIBA CUC/UP . WE C • iai7 2 4 1 _ 0 Q ia0 D 1 7 ■ 1 ~ - 5 Z 'J 3 '0 3 TOSHIBA TMP82C255A/TMP82C265A CMOS PROGRAMMABLE PERIPHERAL INTERFACE TMP82C255AN-2 / TMP82C265AF-2 TMP82C255AN-10 / TMP82C265AF-10

TMP821DR

Abstract: TMP821DRG4
Contextual Info: TMP821 www.ti.com SLDS152 – JANUARY 2008 TWO-PHASE HALF-WAVE MOTOR PREDRIVER FEATURES 1 • • • • Built-In Lock Detection and Rotational Speed Sensing Mechanisms Compact 8-Pin Package Reduces Number of External Components Required Automatic Restart When Motor Lock Is

p8255a

Abstract: P8255AH P8255 PC317
Contextual Info: TO SH IBA TMP82C55A CMOS PROGRAM M ABLE PERIPHERAL INTERFACE TMP82C55AP-2/TMP82C55AM-2 TMP82C55AP-10/TMP82C55AM-10 1. GENERAL DESCRIPTION AND FEATURES T h e T M P 8 2 C 5 5 A h e r e in a f te r r e f e r re d to as P P I is a CM OS h ig h S p eed p rogram m able in p u t/o u tp u t in terface w ith th re e 8 -b it I/O ports. 24 I/O P o rts are divided

P82c53

Contextual Info: T O S H IB A TMP82C53 PRO GRAM M ABLE INTERVAL TIMER TMP82C53P-2 1. GENERAL DESCRIPTION The TM P82C 53P-2 h erein after referred to as TM P82C53 is a p ro g ra m m a b le counter/tim er. It is organized as 3 independent 16 bit counters, each operates w ith a

MPU85-9

Abstract: P82C53
Contextual Info: TOSHIBA TMP82C53 PRO GRAM M ABLE INTERVAL TIMER TMP82C53P-2 1. GENERAL DESCRIPTION T he T M P82C 53P-2 h e re in a fte r referred to as TM P82C 53 is a p ro g ra m m a b le counter/tim er. It is organized as 3 indepen dent 16 b it counters, each operates w ith a

82C79

Abstract: TMP82C79 SSOP40 fifo ram 8bit TMP82C79P-2 line scan sensor SSOP40 package 16X4 MPU85-272 D-B73C
Contextual Info: T O S H IB A TMP82C79 P R O G R A M M A B LE KEYBO ARD /D ISPLAY INTERFACE TMP82C79P-2/TMP82C79M-2 1. G EN ER A L DESCRIPTION The TM P82C79P-2/M-2 hereinafter referred to as TM P82C79 is a programmable keyboard/display interface. The keyboard portion can provide a scanned interface up to

TMP82C79P-2

Abstract: 82c79 TMP82C79 fifo ram 8bit ssop40 16X4 TMP82C79M-2 toshiba signal multiplexing D-B73C
Contextual Info: T O S H IB A TMP82C79 P R O G R A M M A B LE KEYBO ARD /D ISPLAY INTERFACE TMP82C79P-2/TMP82C79M-2 1. G EN ER A L DESCRIPTION The TM P82C79P-2/M-2 hereinafter referred to as TM P82C79 is a programmable keyboard/display interface. The keyboard portion can provide a scanned interface up to

TMP82C54

Abstract: TMP82C53P-2 TMP82C54M-2 TMP82C54P-2 TGS 832 MPU85-9
Contextual Info: T O S H IB A TMP82C54 P R O G R A M M A B L E INTERVAL TIMER T M P 82C 54P -2 / T M P 8 2 C 5 4 M -2 The TM P82C54P-2 TM P82C54M -2 hereafter called the TM P82C54 is a low power, CMOS general-purpose programmable timer/counter. The TM P82C54 consists of 3 independent 16-bit counters to implement high-speed

TCA 3089

Abstract: tmp82c55* toshiba westinghouse co 11 tcc TMP82C255A TMP82C255AN TMP82C255AN-2 TMP82C265A TMP82C265AF TMP82C255AN-10 TMP82C55AX2
Contextual Info: TOSHIBA TMP82C255A/TMP82C265A CMOS PROGRAMMABLE PERIPHERAL INTERFACE TM P82C 255AN -2 /TM P 82C 265A F -2 TM P 82C 255A N -10 / TM P82C 265AF-10 1. GENERAL DESCRIPTION A N D FEATURES The TMP82C255A/TMP82C265A is a CMOS high speed programmable input/output

TMP8255AP-5

Abstract: TMP8255AP5 TMP8255A
Contextual Info: TO SH IBA TMP8255A PRO GRAM M ABLE PERIPHERAL INTERFACE TMP8255AP-5 1. GENERAL DESCRIPTION AND FEATURES The TMP8255A hereinafter referred to as PPI is a high Speed program m able input/output interface w ith three 8-bit I/O ports. 24 I/O ports are divided into two

TMP82C43P

Abstract: Intel 8243 TMP82C43
Contextual Info: T O S H IB A TMP82C43P C M O S INPUT/O UTPUT E X P A N D E R TLCS-48C TM P82C43P 1. G E N E R A L D ESCRIPTIO N A N D FEATURES The T M P 82C 43P is an in put/output exp an d er d esign ed sp ecifically to provide a low cost m ean s of I/O exp an sion for the T L C S -48C fam ily.

MPU85-207

Contextual Info: TOSHIBA TMP82C255A/TMP82C265B CMOS PRO G RAM M ABLE PERIPHERAL INTERFACE. TMP82C255AN-2 /TMP82C265BF-2 TMP82C255AN-10 /TMP82C265BF-10 1. GENERAL DESCRIPTION AND FEATURES The TMP82C255A/TMP82C265B is a CMOS high speed program m able input/output interface w ith six 8-bit I/O ports. The function, is almost equivalent to TMP82C55AX 2.

TMP82C54P2

Contextual Info: TO SH IBA TM P82C54 PRO GRAM M ABLE INTERVAL TIM ER TMP82C54P-2 /TM P82C54M -2 The TM P82C54P-2 TM P82C54M -2 hereafter called the TM P82C54 is a low power, CM OS general-purpose program m able tim er/counter. The TM P82C54 consists of 3 independent 16-bit counters to im plem ent high-speed

Contextual Info: TMP821 w w w .t i.c om SLDS152 – JANUARY 2008 TWO-PHASE HALF-WAVE MOTOR PREDRIVER FEATURES 1 • • • • Built-In Lock Detection and Rotational Speed Sensing Mechanisms Compact 8-Pin Package Reduces Number of External Components Required Automatic Restart When Motor Lock Is

TMP82C265BF-10

Abstract: TMP82C255A TMP82C255AN-10 TMP82C255AN-2 tmp82c265bf tmp82c55* toshiba MPU85 TMP82C265BF-2
Contextual Info: T O S H IB A TMP82C255A/TMP82C265B CMOS PROGRAMMABLE PERIPHERAL INTERFACE T - 5 2 .- 3 3 - S 3 TMP82C255AN-2 /TMP82C265BF-2 TMP82C255AN-10 /TMP82C265BF-10 1. GENERAL DESCRIPTION AND FEATURES The TMP82C255A/TMP82C265B is a CMOS high speed programmable input/output

PC1310

Contextual Info: TMP82C265BF-2 1/3 IL00 * C-MOS PROGRAMMABLE PERIPHERAL INTERFACE 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VCC (+5V) 64 63

Contextual Info: TMP821 www.ti.com SLDS152 – JANUARY 2008 TWO-PHASE HALF-WAVE MOTOR PREDRIVER FEATURES 1 • • • • Built-In Lock Detection and Rotational Speed Sensing Mechanisms Compact 8-Pin Package Reduces Number of External Components Required Automatic Restart When Motor Lock Is

Contextual Info: TOSHIBA TMP8251A PROGRAMM ABLE COMMUNICATION INTERFACE TM P8251AP 1. GENERAL DESCRIPTION The TMP8251AP is the industry standard Universal Synchronous/Asynchoronous Receiver/Transmitter USART that is fabricated using N-channel silicon gate MOS technology.

Contextual Info: T O S H IB A TMP82C59A TOSHIBA MOS TYPE DEGITAL INTEGRATED CIRCUIT Silicon Monolithic CMOS Silicon Gate TMP82C59AP-2/TMP82C59AM-2 PROGRAM M ABLE INTERRUPT CONTROLLER 1. GENERAL DESCRIPTION T M P 82C 59A P -2/A M -2 h ere in after referred to a s T M P 8 2 C 5 9 A is a p ro gram m ab le

A-PC06

Abstract: TMP82C255A TMP82C255AN-10 TMP82C255AN-2 TMP82C265A TMP82C265AF-10 MPU85
Contextual Info: TO SH IB A TMP82C255A/TMP82C265A CM OS PR O G R A M M A B LE PERIPH ER A L INTERFACE TMP82C255AN-2 /TMP82C265AF-2 TMP82C255AN-10 / TMP82C265AF-10 1. G EN ER A L DESCRIPTION AN D FEATURES The TMP82C255A/TMP82C265A is a CMOS high speed programmable input/output

TMP82C53P

Abstract: tmp82c53 TMP82C53P-2 Binary counter simple MPU85-90
Contextual Info: TOSHIBA TMP82C53 PRO GRAM M ABLE INTERVALTIM ER TMP82C53P-2 1. GENERAL DESCRIPTION The T M P82C 53P -2 h ere in afte r referred to a s T M P82C 53 is a p ro g ra m m a b le counter/tim er. It is organized as 3 independent 16 bit counters, each operates with a