TME 57 Search Results

CK505

Abstract: SRC11 9ERS3165BKILF ics TSSOP-64 intel amt bios
Contextual Info: DATASHEET Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock Recommended Application: Industrial temperature CK505 compatible clock for embedded systems PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SEL PCI5_F/ITP_EN GNDPCI VDD48 USB48M/FSLA

9LPR501

Abstract: CK505 ICS9LPR501 VDD96
Contextual Info: ICS9LPR501 Integrated Circuit Systems, Inc. 64-pin CK505 w/Fully Integrated Voltage Regulator PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/TME PCI3 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 DOTC_96/SRCC0 GND VDD SRCT1/SE1 SRCC1/SE2

MCF5200

Abstract: programmers reference manual EWS300-24 instruction manual
Contextual Info: TABLE OF CONTENTS Paragraph Number Tme Page Number Section 1 Introduction 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.2 1.2.1 1.2.2 1.2.3 1.3 1.4 1.4.1 1.4.2 Integer Unit User Programming Data Registers D7 - D 0 . 1-1

qe-2000

Abstract: TME-2000 FE-1000 fe1000 traffic 1517-pin QE2000 BME-3200
Contextual Info: TME-2000 INTEGRATED SWITCH AND TRAFFIC MANAGER SUMMARY OF BENEFITS FEATURES • Bandwidth • Optimized for the Metro-Ethernet and packet aggregation markets • Supports 20 Gbps traffic throughput • Line-rate for all packet sizes • Low-cost DDRII-DRAM for deep buffering

CK505

Abstract: CK505-compliant ICS9LPR501 VDD96 CPUSKEW20
Contextual Info: ICS9LPR501 Integrated Circuit Systems, Inc. 64-pin CK505 w/Fully Integrated Voltage Regulator PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/TME PCI3 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 DOTC_96/SRCC0 GND VDD SRCT1/SE1 SRCC1/SE2

broadcom switch user manual

Abstract: 10G-XFP MPC8540 TME-2000 FE-1000 queuing theory
Contextual Info: METROBOX REFERENCE DESIGN METRO-ETHERNET SOLUTION SUMMARY OF BENEFITS FEATURES • The MetroBox™ is a complete reference design with 24 GbE ports and two 10 GbE ports. • It is based on Broadcom's programmable FE-1000 packet processor, and the high-end TME-2000 queuing engine, both

Contextual Info: 4 3 TMe dooumwit ia too proporlp of Amptanol Corporation and ti doirorod on mar • lo net to bo dbomodt repreduood or wad. In irmHie other toon Amphonol Corporation rritootri tti ^rtof eeneori, ft tl right lo grantod to dtootooe A. NOTE: 1. 2. 3. 4. 5. 6.

Contextual Info: 24 Pin DIP Passive Delay Lines OUTPUT RISE TME nS Max. TAP TO TAP DELAYS nS TOTAL DELAY nS ±5% or ±2 nS t Zo OHMS ±10% PART NUMBER ATTEN Max. % : 1.0 ±0.2 2.5 ±0.5 5.0 ±1.0 10.0 ±1.0 1.0 ±0.2 2.5 ±0.5 5.0 ± 1.0 10.0+1.0 25.0 ±2.5 50.0 ± 5.0 1.0 ±0.2

EPA059-1000B

Abstract: EPA059-100A EPA059-100B EPA059-200A EPA059-200B EPA059-20A EPA059-20B EPA059-20C EPA059-500B EPA059-50A
Contextual Info: 24 Pin DIP Passive Delay Lines Zo OHMS ±10% TOTAL DELAY nS ±5% or ±2 nS† 50 50 50 50 100 100 100 100 100 100 200 200 200 200 200 TAP TO TAP DELAYS nS 20 50 100 200 20 50 100 200 500 1000 20 50 100 500 1000 OUTPUT RISE TME nS Max. 1.0 ± 0.2 2.5 ± 0.5

Contextual Info: 24 Pin DIP Passive Delay Lines Zo OHMS ±10% 50 50 50 50 100 100 100 100 100 100 200 200 200 200 200 TOTAL DELAY NS ±5% or ±2 NS TAP TO TAP DELAYS NS 20 50 100 200 20 50 100 200 500 1000 20 50 100 500 1000 OUTPUT RISE TME NS MAX 1,± 0.2 2.5 ±0.5 5 ± 1.0

EPA059-1000B

Abstract: EPA059-100A EPA059-100B EPA059-200A EPA059-200B EPA059-20A EPA059-20B EPA059-20C EPA059-500B EPA059-50A
Contextual Info: 24 Pin DIP Passive Delay Lines Zo OHMS ±10% TOTAL DELAY nS ±5% or ±2 nS† 50 50 50 50 100 100 100 100 100 100 200 200 200 200 200 250 TAP TO TAP DELAYS nS 20 50 100 200 20 50 100 200 500 1000 20 50 100 500 1000 400 OUTPUT RISE TME nS Max. 1.0 ± 0.2 2.5 ± 0.5

20-Microseconds

Abstract: DS022-2 DS0222
Contextual Info: LTR A 2 5 BY DESCRIPTIO N DATE APPRO VED REVISED P£X £ C M / O ï à DAICO TME «ra ttt& T IO N M C L O M O HCM W WAS O ftM iN A T O « t amo i t t h c p m o k r t y of djuco m m m t m c s , ano e x c e t t FON RMMTS CXPftC ttLT MAHTCO TO THC UNITED STATU

TME 57

Contextual Info: ^ E D I EDI8F16512C S12Kx16 SRAM Module ElECTUONC Œ SG N S N C .i 512KX16 Static RAM CMOS, Module Features 512Kx16bitCMOS Static Random Access Memory • Access Times 70 thru 100ns • Data Retention Function EDI8F16512LP • TTL Compatible Inputs and Outputs

3DQ10

Abstract: ICC1 EDI8L32512C20AI
Contextual Info: m EDI8L32512C u 512KX32 SRAM Module aECTROMC DE9GN1 MC 512Kx32CMOSHigh Speed Static RAM Features DSP Memory Solution The EDI8L32512C is a high speed, 5V, 16 megabit SRAM. • Motorola DSP96002 The device is available with access times of 12,15,17 and 20ns allowing the creation of a no wait state DSP memory

Contextual Info: M D EDI9F32256C I B EO RO N C CC9GNI MC. 256Kx32 SRAM Module Features 256Kx32 Static RAM CMOS, High Speed Module 256Kx32 bit CMOS Static The EDI9F32256C is a high speed 8 megabit Static RAM module Random Access Memory organized as 256K words by 32 bits. This module is constructed from

Contextual Info: MHTEPTEKC www.i-t.su info@i-t.su Ten: O f l H o p a 3 p f l A H b i e 495 739-09-95, 644-41-29 c e M M c e rM e H T H b ie M H flM K aT opbi 57 MM BbicoTa 3HaKa : 57 mm np0M3B0AMTenb : Kingbright flnana30H cnnbi CBeTa yKa3aH npH TOKe 10 mA. Kofl: SA23 SA23

Contextual Info: EDI8L32256C M D I ELEC1ROMC D 69G N & M C 2S6Kx32 SPAM Module PRELIMINARY 256Kx32 CMOS High Speed Static RAM Features The EDI8L32256C is a high speed, high performance, four megabit density Static FtAM organized as a 256Kx32 bit 256Kx32 bit CMOS Static array.

SP000409156

Abstract: keil omnivision EVALUATION BOARD PMA7110 PMAx110-434-5-USB-RF 915-10 TOKO LSM767 C51 Family Lambda Sensor sirius c20
Contextual Info: PMA71xx/PMA51xx SmartLEWIS MCU PMA Evaluation Kit User Guide Rev. 1.0, 2009-12-16 Wireless Control Edition 2009-12-16 Published by Infineon Technologies AG 81726 Munich, Germany 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or

tme 126

Contextual Info: HB56UW272E-7B/8B 2,097,152-Word x 72-Bit High Density Dynamic RAM Module 168-pin JEDEC Standard Outline Buffered 8BYTE DIMM HITACHI Preliminary - Rev. 0.0 Feb. 02, 1996 Description The HB56UW272E belongs to 8 Byte DIMM Dual In-line Memory Module family, and has been

MTB75N03HDL

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICA-L DATA - Product Preview MTB75N03HQL HDTMOSTM EMFETTM Power FET High Density Preferred Device Wtorola NnChanne! Enhancement=Mode Silicon Gate This advanced high-cell density HDTMOS E-FET is designed to withstand high energy in the avalanche and mmmutation

Contextual Info: EDI8F32256C ^ E D I 256Kx32 SRAM Module ELECTRONIC DESIGN! N C l Features 256Kx32 Static RAM CMOS, High Speed Module 256Kx32 bit CMOS Static The EDI8F32256C is a high speed 8 megabit Static RAM Random Access Memory • module organized as 256K words by 32 bits. This module is

TME 57

Abstract: QF 45002 EDI8F32128C CJQ20
Contextual Info: ^ E D I _ EDI8F32128C ì28Kx32 S R A M Module ELiciRONc e *» -« 128Kx32 Static RAM Features CMOS, High Speed Module 128Kx32 bit C M O S Static The EDI8F32128C is a high speed 4 megabit Static RA M Random Access Memory

Contextual Info: EDI8L32128C ^ E D I ELECTRONIC CC96NS. N C | 128Kx32 SRAM Module 128Kx32 CMOS High Speed Static RAM F e a tu re s 128Kx32 bit CMOS Static Random Access Memory Array • Fast Access Times: 12*, 15,17,20, and 25ns • Individual Byte Enables • User Configurable Organization

Contextual Info: m o EDI5M3232C i ELfCTPOMCOESGtëNC. 32Kx32 EEPROM 32Kx32 CMOS EEPROM Module Features 32Kx32 bit CMOS The EDI5M3232C is a high speed, high performance, one Electrically Eraseable Programmable megabit density EEPROM module organized as 32Kx32 Read Only Memory Module