TL O71 Search Results

WIRING diagram USB to rca CABLE

Contextual Info: [AKD7742-B] AKD7742-B AK7742 Evaluation Board Rev.1 GENERAL DESCRIPTION The AKD7742-B is an evaluation board for AK7742, which is a highly integrated audio processor including a stereo ADC with 6ch input selector, two stereo DAC and an audio DSP. This board is composed of a

Contextual Info: [AKD7742-B] AKD7742-B AK7742評価ボードRev.1 概 要 AKD7742-Bは3系統入力セレクタ付き2ch ADC,4ch DAC,オーディオ用DSPを内蔵したオーディオプロ セッサー AK7742の評価用ボードです。このボードはメインボードとサブボードの2枚構成となってお

ec 6sl

Contextual Info: NOVEMBER 20, 1996 TEST REPORT #96281 QUALIFICATION TESTING CLT/TMM SAMTEC CORPORATION APPROVED BY: MAX PEEL PRESIDENT AND DIRECTOR OF ADVANCED RESEARCH CONTECH RESEARCH, INC. Contech Research . CERTIFICATION This is to certify that the evaluation described herein was

321 tlt 131

Abstract: 290H TLCS-900 LTZF H8050
Contextual Info: TOSHIBA TLCS-900 CPU LINK < Link m dst, num 7 9 y 7 7 V - A « 4 Wi, > fP : —XSP <-dst, dst<-XSP, XSP<-XSP + num M 9 y ? 7 9 y 7 ^ ^ 7 9XSP<D\H^ £ *i£ t o ^'dst^fsjäl £ ti i 1 0 MÎ â. K 7 9 y 7 ^ 4 7 9 XSP<7)# t numW F*üW è)^ÎJD#£*i, X 9 y 7

S1D15605

Abstract: Display Controller S1D15206 S1D15B01 Acc 2089 S1D15202F yd 2030 ic 5 pins S1D15202F00A s1d15208f op amp ua 743
Contextual Info: MF424-21 S1D15000 Series Technical Manual IEEE1394 LCD driverController with RAM S1R75801F00A S1D15000 Series Technical Manual S1D15000 Series Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/

zilog 3730

Abstract: zilog 3055 application SED1575 R24 marking code dual SED1575T3A SED1560TQA D1565 SED1577 SED1565DBB SED1500
Contextual Info: MF424-18 s ie r e M S A 0 R th i 5 er w E S 1 D Dd riv LC lM a nic ch Te al u an SEIKO EPSON CORPORATION NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

Contextual Info: ADVANCE MICRON 8 MEG TECHNOLOGV INC. DRAM MODULE X MT36LD872 X 72 DRAM MODULE 8 MEG x 72 64 MEGABYTE, ECC, 3.3V, FAST PAGE OR EDO PAGE MODE FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • JEDEC- and industry-standard ECC pinout in a 168pin, dual-in-line memory module (DIMM)

CY37384

Contextual Info: PRELIMINARY C Y37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns Product-term clocking • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os

xc4000 pin

Abstract: 57B8 dsp o212 PQ304 o4413 atmel 144
Contextual Info: Features • Ultra High Performance • • • • • • • • – System Speeds to 100 MHz – Array Multipliers > 50 MHz – 10ns Flexible SRAM – Internal 3-State Capability in each Cell FreeRAM – Flexible, Single/Dual Port, Sync/Async 10 ns SRAM

pd70325

Abstract: stm cl-11 SE 7889 UPD70325-10 IC-7889 NEC uPD70325 U1285 ic7889 PD70325L-10 l6sr
Contextual Info: -J— S 7 • 5 /— h M O S Ä3Ä1ÜS& M O S Integrated C ircuit j u P D 7 0 3 2 5 V25 + 1 6 / 8 t£ y h • ¿¿PD70325 £i J£f f c V25 + ü , tu is 7 > 1 6 t ' • • / l ' C P U , RAM, 7 ° - ' y i ) T ) V - 4 > ^ 7 i - X , ? -Í -v, D MA 3 > ) - u - 7 ,

n20s

Abstract: CY3600 CY37512 CY37512V 0228l
Contextual Info: C Y37512 PR ELIMINA RY UltraLogic 512-Macrocell ISR™ CPLD — tc o = 6 ns Features • P ro d uct-term clocking • 512 m a cro c ells in 32 logic blo cks • IEEE 1149.1 JTAG b o u n d a ry scan • In-S ystem R ep ro g ra m m ab le ™ IS R ™ • P ro g ram m ab le slew rate control on ind ividu al l/O s

PJ 52

Abstract: U1615 U18-18 u1515 U23D-43 U176 U21-18 u1818 L115 U218
Contextual Info: Enhanced Memory Systems Inc. DM1M64DT6/DM1M72DT6 Multibank EOO EDRAM 1Mb x fflM b x 72 Enhanced DRAM DIMM Product Specification Features • l 6Kbytes SRAM Cache Memory for 12ns Random Reads Within Eight Active Pages Multibank Cache ■ Fast 8Mbyte DRAM Array for 30ns Access to Any New Page

tl o84

Abstract: AT60054QI fyl 5042 ugc m6 90 v-0 tl o71 TL O74 AT6002 AT6003 AT6005 AT6010
Contextual Info: AT6000 Series Features • • • • • • • High Performance System Speeds > 100 MHz Flip-Flop Toggle Rates > 250 MHz 1.2 ns Input Delay 3.5 ns Output Delay Thousands of Registers Cache Logic Design Complete/Partial In-System Reconfiguration No Loss of Data or Machine State

M5M82C51AP

Abstract: M5M82C51AP/FP/J
Contextual Info: ETE D • bEM^asa O G I 4T S 1 2 ■ M ITSU B ISH I LSIs M5M82C51AP/FP/J MITSUBISHI HICMPTR/MIPRC CMOS PROGRAMMABLE COMMUNICATION INTERFACE T - r7 5 -3 '7 '0 7 DESCRIPTION The M5M82C51AP is a universal synchronous/asynchronous receiver/transmitter (USART) 1C chip designed for data

7DCR

Contextual Info: ^ 2 iL G 5 P r o d u c i S opì i'ir.itioi Z84C90 CMOS Z80 KIO Serial/Parallel/Counter/Timer FEATURES: • • • • • Two independent synchronous/asynchronous serial channels. Three 8 -bit parallel ports. Four Independent counter/timer channels. On-chip clock oscillator/driver.

d4184

Abstract: transistor N14 193 atmel application note AT6002 AT6003 AT6005 AT6010
Contextual Info: Features • High-performance • • • • • • • • • – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os Thousands of Registers Cache Logic Design

TL O74

Abstract: AT6002 AT6003 AT6005 AT6010
Contextual Info: AT6000/LV Series Features • • • • • • • • • • High Performance System Speeds > 100 MHz Flip-Flop Toggle Rates > 250 MHz 1.2 ns/1.5 ns Input Delay 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os Thousands of Registers Cache Logic Design

Contextual Info: Lattice T'Aie Lattice ispLSI and pLSI 2000 Family ï i I Corporation Features_ J Introduction to ispLSI and pLSI 2000 Family ispLSI and pLSI 2000 Family □ 154 M Hz System Perform ance □ 5.5 ns Pin-to-Pin Delay □ High Density 1,000-6,000 PLD Gates

32x32 multiplier verilog code

Abstract: W 20 81 210 16X16 32X32 40X40 AT40K05 AT40K10 AT40K20 AT40K40 XC4000
Contextual Info: Features • Ultra High Performance • • • • • • • • – System Speeds to 100MHz – Array Multipliers > 50MHz – 10ns Flexible SRAM – Internal 3-State Capability in each Cell FreeRAM – Flexible, Single/Dual Port, Sync/Async 10ns SRAM

triacs bt 804 600v

Abstract: UR720 1N4465 AO110 diode 1N539 2N3750 Unitrode discrete databook 2N6138 CM104 unitrode 679 BRIDGE rectifier
Contextual Info: UNITRODE SEMICONDUCTOR DATABOOK 1976 C opyright 1976 U nitrode C orporation, W atertown, MA. A ll rights reserved. INTRODUCTION From its inception 16 years ago, Unitrode has acquired a reputa­ tion for maintaining an unusually high level of quality, perfor­

scr5 1625

Abstract: AT94K preliminary 9B28
Contextual Info: Features • Monolithic Field Programmable System Level Integrated Circuit FPSLIC • • • • • • • • • • • • • • – AT40K SRAM-based FPGA with Embedded High-performance RISC AVR Core and Extensive Data and Instruction SRAM

SCR avr SCHEMATIC circuit diagram

Abstract: ATMEL AVR pid Adaptive temperature control AT94K preliminary 1001 dl pwm ICS scr FIR 3D 41 atmel 1138* datasheet fcx0 AT17 AT40K AT94K05
Contextual Info: Features • Monolithic Field Programmable System Level Integrated Circuit FPSLIC • • • • • • • • • • • • • – AT40K SRAM-based FPGA with Embedded High-performance RISC AVR Core and Extensive Data and Instruction SRAM 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™