TIM CS Search Results

digital stopwatch

Abstract: 6-Digit Electronic Stopwatch LITRONIX dl DF213 LITRONIX DF213CJ 18 pin led display ic three digit STOPWATCH 8 DIGIT Beckman Industrial BECKMAN
Contextual Info: designed fo r . • • B E N E F IT S T w o Tim ing Fu n ction s in O ne 1C • Sports Tim ing Auto Racing, Track, Sw im m ing, Rodeo, Sailing , Football, Soccer ■ Industrial Tim ing ^ Testing, Time-Motion Studies, Process Tim ing ■ Scientific Tim ing

HYB51

Contextual Info: SIEM ENS HYB 511002-10/-12 1 048 576 Bit Static Column Dynamic RAM 1 048 576 w o rd s by 1 b it o rg a n iz a tio n Fast access and c ycle tim e 100 ns access tim e 190 ns c ycle tim e HYB 511002-10 120 ns access tim e 220 ns c ycle tim e (HYB 511002-12)

Contextual Info: IBM0165800B 8M x 8 12/11 DRAM Features • 8,388,608 word by 8 bit organization • Performance: -50 -60 jtRAC ! RAS Access Tim e 50ns 60ns jtcAC ! CAS Access Tim e 13ns ' 5ns ;1aa ! Column Address Access Tim e I 25ns 30ns |1rc I Cycle Tim e 90ns ! 11 0 ns i

CERAMIC LEADLESS CHIP CARRIER LCC 44

Abstract: atmel at28C010 AT28C010 5962-38267
Contextual Info: Features * Fast Read Access Tim e -1 2 0 ns * Autom atic Page W rite Operation Internal Address and Data Latches for 128-Bytes Internal Control Tim er * Fast W rite Cycle Tim e Page W rite Cycle Tim e -1 0 ms Maximum 1 to 128-Byte Page W rite Operation * Low Power Dissipation

41257

Abstract: H R C M F 2J 225
Contextual Info: SIEMENS HYB 41257-12/-15/-20 262,144-Bit Dynamic Random Access Memory RAM • Fast nibble m ode on read and w rite cycles via addresses A8 row and A8 colum n 30 ns access tim e 65 ns cycle tim e (HYB 41257-12) 40 ns access tim e 80 ns cycle tim e (HYB 41257-15)

0a0c1

Contextual Info: Features * Single Voltage Operation - 5V Read - 5V Reprogramming * Fast Read Access Tim e - 90 ns * Internal Program Control and Tim er * 8K Bytes Boot Block With Lockout * Fast Erase Cycle Tim e - 1 0 seconds * Byte-By-Byte Programming - 50 ps/Byte * Hardware Data Protection

Contextual Info: MOSEL VI TEL IC PRELIMINARY V53C516400A 4M x 4 FAST PAGE MODE CMOS DYNAMIC RAM V53C516400A 50 60 Max. R A S Access Tim e, Ì raq 50 ns 60 ns Max. Colum n Address Access Tim e, (Ì q aa ) 2 5 ns 30 ns Min. P age M ode C ycle Tim e, (tpc) 3 5 ns 4 0 ns Min. R ead /W rite C ycle Tim e, (tRC)

MK2147-70

Abstract: MK2147-55 vs5-24v MK2147 MK2147-85
Contextual Info: MOSTEK 4K x 1 -BIT STATIC RAM M K 2147 J -55/70/85 FEATURES □ Address Activated static m em ory— no clock or tim in g strobe required □ Sicaled Poly 5™ technology □ Industry standard 18-pin dip configuration □ Access tim e equal cycle tim e

Contextual Info: IBM0165405B IBM0165405P 16M x 4 12/12 EDO DRAM Features • 16,777,216 word by 4 bit organization Read-Mod ify-Write • Single 3.3 ± 0.3V power supply Performance: -50 -60 I rac RAS Access Tim e 50 ns 60ns tcAC GAS Access Tim e 13ns 15ns •*AA ; Colum n Address Access Tim e

faa11

Abstract: 5118165 d lt 7210
Contextual Info: SIEMENS 1M X 32-Bit Dynamic RAM Module Hyper Page Mode - EDO Version HYM 321005S/GS-50/-60 Advanced Inform ation • 1 048 576 w ords by 32-bit organization • Fast access and cycle tim e 50 ns access time 84 ns cycle tim e (-50 version) 60 ns access tim e

6s3b

Abstract: Q67100-Q2098 Q67100-Q2099
Contextual Info: SIEM EN S 8M X 32-Bit EDO-DRAM Module HYM328025S/GS-50/-60 Advanced Inform ation • 8 388 608 words by 32-bit organization • Fast access and cycle tim e 50 ns access time 84 ns cycle tim e -50 version 60 ns access time 104 ns cycle tim e (-60 version)

Contextual Info: TEXAS INSTR -CASIC/MEMORY} Ì7 Ô Ë | flìtlTES D074Ô31 □ 262,144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY FEBRUARY 1988 262,144 x 4 Organization JD PACKAGE TOP VIEW Performance Ranges: AC C ESS AC C ESS AC C ESS TIM E TIM E TIM E • e 4 5 ns *a(CA)

Contextual Info: IBM11 D4475B IBM11 E4475B IBM11D8475B IBM11E8475B 4M/8M x 32 Desktop ECC-on-SIMM Features • 72-Pin JEDEC Standard Single-In-Line Memory Module • Performance: : -6R : I rac RAS Access Tim e ; 60ns : tc A C CAS Access Tim e : 18ns : U a I rc t|HPC A ccess Tim e From Address ; 30ns ;

AA S50

Contextual Info: SIEM EN S 4M x 32-Bit Dynamic RAM Module HYM 324020S/GS-50/-60 Advanced Information • 4 194 304 words by 32-bit organization alternative 8 388 608 words by 16-bit • Fast access and cycle tim e 50 ns access time 90 ns cycle tim e (-50 version) 60 ns access tim e

1000va transformer

Abstract: power transformer class B transformer 230vac ul 506 class 130 61558-1 UL506 UL-506 TIM 1000 en 61558-2-4 1000VA
Contextual Info: TIM 1000 Revised : 03.2002 Product Type No.: Isolating Transformer TIM 1000 Schematic Plan Technical Details Safety Standards Designated Voltage Designated Voltage Designated Current Designated Frequency Output Power Protection Index Protection Class Insulation Class

BU2302

Abstract: BU2305 BU2305F X222 BU2302F U2305F
Contextual Info: Standard ICs Standard ICs GR timer BU2302/B U2302F/B U2305/B U2305F The BU 2302/F and B U 2305/F are general-purpose ICs used in tim ers. The tim er off tim e is based on the oscillation frequency that is determ ined by the external CR connected to the internal oscillator circuit.

500va transformer

Abstract: 500VA UL-506 217A transformer class 2 UL506 Class b 130C transformer transformer 230vac
Contextual Info: TIM 500 Revised : 03.2002 Product Type No.: Isolating Transformer TIM 500 Schematic Plan Technical Details Safety Standards Designated Voltage Designated Voltage Designated Current Designated Frequency Output Power Protection Index Protection Class Insulation Class

800VA

Abstract: Class b 130C transformer transformer parallel UL506 transformer 230vac
Contextual Info: TIM 800 Revised : 03.2002 Product Type No.: Isolating Transformer TIM 800 Schematic Plan Technical Details Safety Standards Designated Voltage Designated Voltage Designated Current Designated Frequency Output Power Protection Index Protection Class Insulation Class

Contextual Info: MOSEL VITELIC V54C365164VA HIGH PERFORMANCE 3.3 V 0 L T 4 M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 PRELIMINARY 8 10 System Frequency fCK 125 MHz 100 MHz Clock Cycle Tim e (tcK 3 ) 8 ns 10 ns Clock Access Tim e (tAC3) CAS Latency = 3 7 ns 8 ns Clock Access Tim e (tAC2) CAS Latency = 2

Contextual Info: Preliminary information •■ AS4LC256K16E0 II 3.3V 256KX16 CMOS DRAM EDO Features • O rganization: 2 6 2 ,1 4 4 w o rd s x 16 bits • H igh speed - 3 5 / 4 5 / 6 0 ns RAS access tim e - 1 7 / 2 0 /2 5 ns c o lu m n address access tim e - 7 / 1 0 / 1 0 ns CAS access tim e

IC 4027 pin diagram

Abstract: IC CD 4027 purpose of IC 4027 MK4027 MK4027-1 MK4027-3 ram 4027 4096X1-BIT IC 4027 501C
Contextual Info: MQSTEK 4096x1-BIT DYNAMIC RAM M K 4 0 2 7 J/N -2 /3 F E A TU R E S □ Ind ustry standard 16-pin DIP (M K 4096) co n fig u ra tio n □ 120ns access tim e, 320ns cycle (M K 4027-1) 150ns access tim e , 320ns cycle (M K 40 27 -2) 200ns access tim e, 375ns cycle (M K 4027-3)

V53C8256H

Abstract: Wx25
Contextual Info: M O SEL V IT E L IC V53C408H 1M x 4 PAGE MODE CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT HIGH PERFORMANCE PRELIMINARY 40 45 50 60 Max. RAS Access Tim e, tpiAC 40 ns 45 ns 50 ns 60 ns Max. Column Address Access Tim e, (îc a a ) 20 ns 22 ns 24 ns 30 ns Min. Extended Data O ut Page Mode Cycle Tim e, (tPC)

D71054C

Abstract: D71054L 71054-10 PD71054 PD71054C D71054 uPD70208 uPD71054C D70216 V30TM
Contextual Info: MOS INTEGRATED CIRCUII ¿ ¿ P D 7 1 0 5 4 PRO G RA M M A BLE TIM ER/CO U N TER The juPD71054 is a high-performance programmable tim e r/co u n te r designed fo r tim in g co n tro l applications in m icrocom puter systems. The /IPD71054 is fabricated by CMOS technology in order to realize low power consump­

Contextual Info: ECL 4 0 9 6 -B IT BIPOLAR SELF-TIM ED RANDOM ACCESS MEMORY FU JITSU MBM10476RL-9 4 0 9 6 -B IT BIPOLAR S ELF-TIM E D RANDOM ACCESS MEMORY D e c e m b e r, 1988 Edition 1.0 T he Fujitsu M BM 10476RL-9 Is fully d eco ded 4 0 9 6 -b it ECL s e lf-tim e d re a d /w rite