TIC 115 D Search Results

Contextual Info: I CM O S STATIC RAMS 6 4 K 1 6 K X 4-BIT ID T71981S /L ID T71982S /L S eparate Data Inputs and Outputs FEATURES: DESCRIPTION: • S eparate d a ta inp u ts a n d o u tp u ts • IDT71981S/L: o u tp u ts tra ck inp u ts d u rin g w rite m ode • IDT71982S/L: h ig h im p e d a n c e o utp u ts d u rin g w rite m ode

Contextual Info: HIGH-SPEED 3.3V 1K X 8 DUAL-PORT STATIC RAM PRELIMINARY IDT71V30S/L F e a tu re s * High-speed access - * Interrupt flags for port-to-port communication Fully asynchronous operation from either port * Battery backup operation, 2V data retention L Only * TTL-compatible, single 3.3V ±0.3V power supply

Contextual Info: Features ♦ True Dual-Ported memory cells which allow simultaneous access of the same memory location * High-speed access ♦ * * - Industrial 25ns max. - Commercial: 15/20/25/35/55ns (max.) Low-power operation - IDT70261S ♦ ♦ ♦ Active: 750mW(typ.)

Contextual Info: HIGH-SPEED 3.3V 8 K x 16 DUAL-PORT STATIC RAM IDT70V25S/L F e a tu re s * * True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access - * ♦ Commercial: 25/35/55ns max. ♦ ♦ ♦ Low-power operation - IDT70V25S

Contextual Info: » • - SIDE VIEW Infineon t o p v ie w IRMS6115 IRMT6115 115 Kb/s Infrared Data Transceiver Preliminary FEATURES Absolute M axim um Ratings, r A=25°C except w here noted • C om pliant w ith IrDA Specification S upply V oltage Range, all states, Vq q . - 0 . 5 to + 7.0 V

Contextual Info: CM OS RESETTABLE RAM WITH CMOS I 0 LEVELS 64K 8K x 8-BIT IDT71C65S IDT71C65L FEATURES: DESCRIPTION: • Input an d output d ire ctly C M O S -co m p atib le • H ig h -speed (equal a c c e s s an d c y c le time) T h e ID T 7 1 C 6 5 Is a 6 5,536-bit h ig h -sp eed static RAM organized

Contextual Info: ir r te t 51C259H HIGH PERFORMANCE STATIC COLUMN 64K x 4 CHMOS DYNAMIC RAM 5 1 C 2 5 9 H -1 5 Maximum Access Time ns Maximum Column Address Access Time (ns) • Static Column Mode Operation - Continuous data rate over 12 MHz - Random access from address

6116 CMOS RAM

Contextual Info: CMOS STATIC RAM 16K 2Kx 8-BIT IDT6116SA IDT6116LA Integrated Devicelechnol03y Inc FEATURES: DESCRIPTION: • T h e ID T6116S A /LA is a 16,384-bit h ig h -s p e e d s ta tic RAM or­ g an ize d as 2K x 8. It is fa b rica te d u sin g ID T ’s h igh-perform ance,

Contextual Info: Integrated Circuit Systems, Inc. ICS9150-08 Frequency Generator & Integrated Buffers for Pentium/Pro General Description Features The ICS9150-08 generates all clocks required for high speed RISC or CISC m icroprocessor system s such as Intel PentiumPro or Cyrix. Eight different reference frequency

Contextual Info: in t e l 28F016XD 16-MBIT 1 MBIT x 16 DRAM-INTERFACE FLASH MEMORY 85 ns Access Time (tRAC) — Supports both Standard and FastPage-Mode Accesses Multiplexed Address Bus — RAS# and CAS# Control Inputs No-Glue Interface to Many Memory Controllers SmartVoltage Technology

Contextual Info: 1 » i l l 1 IF V 1 F 1 1 U 1 ‘! S y P r • W 0 L HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V3569S F ea tu re s: ♦ True Dual-Ported memory cells which allow simultaneous access of the same memory location ♦ High-speed clock to data access

Contextual Info: IDT70825S/L HIGH SPEED 128K 8K X 16 BIT SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM ) F e a tu re s ♦ ♦ ♦ ♦ * High-speed access * - Military: 35/45ns (max.) - Commercial: 20/25/35/45ns (max.) Low-power operation - IDT70825S - Address based flags for buffer control

Idt7212l

Contextual Info: m m 1 1 ^ 12 x 12-BIT PARALLEL CM O S MULTIPLIER IDT7212L IDT7213L Integrated D eviceTechno!o 3 y. Inc FEATURES: DESCRIPTION: • 12 x 12-bit para lle l m u ltip lie r w ith d o u b le p re cisio n p ro d u ct • H ig h -spe e d : 35ns m a xim u m c lo c k to m u ltip ly tim e

Contextual Info: PRELIMINARY IDT7054S/L HIGH-SPEED 4K x 8 FourPort STATIC RAM * Available in 128 pin Thin Quad Flatpack and 108 pin PGA packages * Industrial temperature range -40°C to +85°C is available for selected speeds Features * High-speed access - Military:25/35ns (max.)

Contextual Info: LM K 02002 LMK02002 Precision Clock Conditioner with Integrated PLL T ex a s In s t r u m e n t s Literature Number: SNAS418 August 2007 Semiconductor LMK02002 Precision Clock Conditioner with Integrated PLL General Description Features The LMK02002 precision clock conditioner combines the

Contextual Info: in te i. 1.0 82961KA W Û T [P^EWOH operate in the non-impact printer environment; how­ ever, many of its features make it extremely wellsuited for other applications. The 82961 KA provides a direct interface between the Intel 80960Kx micro­ processor and system memory, communication

Contextual Info: * 1-Cube PSX Family Data Sheet àÊL F eatures D e s c r ip t io n • SRAM -based, in-system programmable • Switch Matrix The PSX160, PSX128B and PSX96B are SRAM-based bus oriented switches with 160, 128 and 96 l/Os respectively. The devices are manufactured using a 0.6|jm CMOS process and

Contextual Info: in te i 82375EB PCI-EISA Bridge PCEB Provides the Bridge Between the PCI Bus and EISA Bus 32-Bit Data Paths 100% PCI and EISA Compatible — PCI and EISA Master/Slave Interface — Directly Drives 10 PCI Loads and 8 EISA Slots — Supports PCI at 25 MHz to 33 MHz

Contextual Info: 3.3 VOLT CMOS SyncFlFO7 512x36,1,024x36 and 2,048 x 36 Integrated D evice T echnology, Inc. FEATURES: • Available in 132-pin plastic quad flat package PQFP or space-saving 120-pin thin quad flat package (TQFP) • Pin and functionally compatible versions of the 5V

Contextual Info: 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT IDT49C466 IDT49C466A PRELIMINARY Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 64-bit wide Flow-thruE DC • Separate System and Memory Data Input/Output Buses • — Error Detect Time: 10ns

Contextual Info: in te f 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

1892

Abstract: MDIO clause 45
Contextual Info: Integrated Circuit Systems, Inc. ICS 1892 Document Type: Data Sheet Document Stage: Preliminary 10Base-T/100Base-TX Integrated PHYceiver General Features The ICS 1892, an enhanced version of the ICS 1890, is a fu lly integrated, p h ysical-layer d ev ice PHY that is