TI 18J Search Results

AIC23B

Abstract: TLV320AIC23B TLV320AIC23BIPW TLV320AIC23BIRHD TLV320AIC23BPW TLV320AIC23BRHD
Contextual Info: TLV320AIC23B Stereo Audio CODEC, 8Ć to 96ĆkHz, With Integrated Headphone Amplifier Data Manual February 2004 Digital Audio Products SLWS106H IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

Contextual Info: TLV320AIC23 Stereo Audio CODEC, 8Ć to 96ĆkHz, With Integrated Headphone Amplifier Data Manual MAY 2002 Digital Audio Products SLWS106D IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

Contextual Info: TLV320DAC23 Stereo Audio D/A Converter, 8Ć to 96ĆkHz With Integrated Headphone Amplifier Data Manual February 2004 Digital Audio Products SLES001C IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

Contextual Info: TVP5160 NTSC/PAL/SECAM/Component 2x10-Bit Digital Video Decoder Data Manual Literature Number: SLES135A February 2005 − Revised April 2006 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

A115-A

Abstract: C101 SN74GTLPH306 SN74GTLPH306DW SN74GTLPH306DWR
Contextual Info: SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference

Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

mda Signal Generator

Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74ALS2540N OBSOLETE PDIP N 20 TBD Call TI SN74ALS2541DW OBSOLETE

Contextual Info: GeneralĆPurpose LowĆVoltage 1.1 V to 3.6 V I/O 16ĆBit 22ĆKSPS DSP CODEC TLV320AIC11 Data Manual 2002 HPA Product Group SLWS100A IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

C101

Abstract: SN74CB3Q3244 SN74CB3Q3244DW SN74CB3Q3244DWR SN74CB3Q3244RGYR
Contextual Info: SN74CB3Q3244 8ĆBIT FET BUS SWITCH 2.5ĆV/3.3ĆV LOWĆVOLTAGE HIGHĆBANDWIDTH BUS SWITCH SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004 D D D † For additional information regarding the performance characteristics of the CB3Q family, refer to the TI

A115-A

Abstract: C101 SN74GTLP21395 signal path designer
Contextual Info: SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com FEATURES • • • • • • • • • • TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes

Contextual Info: TFP101, TFP101A TI PanelBus DIGITAL RECEIVER SLDS119C - MARCH 2000 − REVISED OCTOBER 2003 D Supports XGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 86 MHz Digital Visual Interface (DVI) Specification Compliant1

Contextual Info: TFP401, TFP401A TI PanelBus DIGITAL RECEIVER SLDS120B - MARCH 2000 − REVISED JUNE 2003 D Supports UXGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 165 MHz Digital Visual Interface (DVI) Specification Compliant1

DIR1703

Abstract: TAS1020 TAS3001 TAS3001C TAS3001CPW TAS3002 TLC320AD77 TUSB3200
Contextual Info: TAS3001C Digital Audio Processor Data Manual March 2004 DAV−Audio Products SLAS226B IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue

Contextual Info: TAS3001C Digital Audio Processor Data Manual March 2004 DAV−Audio Products SLAS226B IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue

Contextual Info: TFP201, TFP201A TI PanelBus DIGITAL RECEIVER SLDS116A - MARCH 2000 − REVISED JUNE 2000 D Supports SXGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 112 MHz Digital Visual Interface (DVI) Specification Compliant1

5 inch LCD panel

Contextual Info: TFP401, TFP401A TI PanelBus DIGITAL RECEIVER SLDS120B - MARCH 2000 − REVISED JUNE 2003 D Supports UXGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 165 MHz Digital Visual Interface (DVI) Specification Compliant1

Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A − DECEMBER 2000 − REVISED OCTOBER 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1

d48 6a2

Abstract: TUSB3410-Q1
Contextual Info: TUSB3410ĆQ1 USB To Serial Port Controller Data Manual 2004 MSP USB SGLS249 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue

TLK3114SA

Contextual Info: TLK3114SA 10ĆGbps XAUI Transceiver Data Manual October 2003 MSDS Multimedia SLLS529B IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue

Signal Path DESIGNER

Contextual Info: www.ti.com SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY FEATURES • • • • • • • • • • • TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes