TERMINATION SENSE Search Results

Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

SC2595

Abstract: SC2595EVB SC2595STRT videocard SR CAP
Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

SR CAP

Abstract: sc2595strt SC2595 SC2595EVB ST EF 017
Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

SR CAP

Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

Contextual Info: LTC4056-4.2 Linear Li-Ion Charger with Termination in ThinSOT FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ U ■ DESCRIPTIO Standalone Li-Ion Charger with Termination Programmable Termination Timer No Sense Resistor or Blocking Diode Required

tp 4056 datasheet

Abstract: 4202 BD TRANSISTOR tp 4056 Li-ion Battery Charger 4056 tp 4056 battery LTC4056-4 4056 charger 4056 16 PIN DIAGRAM M2A MARKING SOT-23 4205 BD TRANSISTOR
Contextual Info: LTC4056-4.2 Linear Li-Ion Charger with Termination in ThinSOT U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Standalone Li-Ion Charger with Termination Programmable Termination Timer No Sense Resistor or Blocking Diode Required

Contextual Info: LP2994 LP2994 DDR Termination Regulator Literature Number: SNVS202B LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

Contextual Info: Obsolete Device LP2994 LP2994 DDR Termination Regulator Literature Number: SNVS202B March 28, 2011 LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

UR5596

Abstract: UR5596L-S08-R UR5596L-S08-T UR5596-S08-R UR5596-S08-T northbridge
Contextual Info: UNISONIC TECHNOLOGIES CO.,LTD UR5596 MOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.

NCP51510

Contextual Info: NCP51510 Product Preview DDR / VTT Termination Regulator 3 Amp − Source/Sink VTT Termination Regulator for DDR−I, −II, −III http://onsemi.com The NCP51510 is a source/sink Double Data Rate DDR termination regulator specifically designed for low input voltage and

Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device which provides a complete solution for DDR termination designs while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5596 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can

SC2595STR

Abstract: SC2595 SC2595EVB SC2595MLTR SC2595STRT 140 ati 030 00 circuit drawing ceramic capacitor, .10nf
Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device which provides a complete solution for DDR termination designs while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM

UR5595L

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.

MP20075

Abstract: MP20075DH-LF DDR3 pcb layout guidelines
Contextual Info: MP20075 3A, 1.3V–3.6V DDR Memory Termination Regulator The Future of Analog IC Technology DESCRIPTION FEATURES The MP20075 precision DDR termination LDO regulator features a precision VREF/2 tracking voltage for accurate termination. The VTT-LDO output can sink/source up to 3A.

ur5596l

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5596 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can be

Contextual Info: LP2998 LP2998 DDR-I and DDR-II Termination Regulator Literature Number: SNVS521G LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of

LP2994

Abstract: LP2994M LP2994MX M08A
Contextual Info: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

LP2994

Abstract: LP2994M LP2994MX M08A
Contextual Info: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description PRELIMINARY Features ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements

MP20075DH

Abstract: Mps 0747 MP20075 MPS 0751 MSOP8E JESD51-7 MO-187
Contextual Info: MP20075 3A, 1.3V–3.6V DDR Memory Termination Regulator The Future of Analog IC Technology DESCRIPTION FEATURES The MP20075 precision DDR termination LDO regulator features a precision VREF/2 tracking voltage for accurate termination. The VTT-LDO output can sink/source up to 3A.

northbridge

Abstract: UR5596 UR5596L-S08-R UR5596L-S08-T UR5596-S08-R UR5596-S08-T
Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5596 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can be

UR5595L

Abstract: UR5595 UR5595L-SH2-R UR5595-S08-R UR5595-S08-T UR5595-SH2-R
Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 MOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM. The device