TD 1862 Search Results

tr 1892

Abstract: HSMI-V2KA1952M01-T HSMI-V2KA Hitachi DSA002700 6075 119 10
Contextual Info: Mar.'10 TBE761 * Pb-free * Halogen and antimony-free 2mm Square Isolator P/N:HSMI-V2KA1952M01-T 1 (2) (3) (4) (5) (6) (7) (8) for for TD-SCDMA TD-SCDMA Specification Frequency Dimensions (1) Series code (2) Size >> V2:2.0x2.0mm (3) Height >> K:1.0mm (4) Model code

HG1930

Abstract: lg s12 MAX2392E MAX2393 max2390 vga balun
Contextual Info: 19-2754; Rev 2; 11/05 KIT ATION EVALU E L B A AVAIL W-CDMA/W-TDD/TD-SCDMA Zero-IF Receivers ♦ Fully Monolithic Direct-Conversion Receivers ♦ Eliminate External IF SAW + IF AGC + I/Q Demod ♦ Meet all 3GPP Receiver’s Standard Requirements with at Least 3dB Margin on Eb/No

J551

Contextual Info: SK4C45 P09TRQNC IN0U9 TREB BELEyEB THE DATA ON THE REÏISHI M O D ECO 18626 DAK BEY 11-16 01 E □BAWWB TD K IS L IA U . SMCE THE TECHNICAL nram M T D N a d vc n phee o f q-w rge. th e u s e r EMPLWB SUCH INFPR m nD N AT H 3 <MN DISCRETIDN AND R B K . PDSTKDNC M 3U5TRS3 ASSUUCS ND

EP2S15

Abstract: EP2S180 EP2S30 EP2S60 EP2S90 SSTL-18 Pin Out For EP2S15
Contextual Info: 5. DC & Switching Characteristics SII51005-4.4 Operating Conditions Stratix II devices are offered in both commercial and industrial grades. Industrial devices are offered in -4 speed grades and commercial devices are offered in -3 fastest , -4, -5 speed grades.

PCI 6601

Abstract: 974-1021 EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 SSTL-18
Contextual Info: 5. DC & Switching Characteristics SII51005-4.3 Operating Conditions Stratix II devices are offered in both commercial and industrial grades. Industrial devices are offered in -4 speed grades and commercial devices are offered in -3 fastest , -4, -5 speed grades.

336 16k 030

Abstract: LVDS fin 1002 Altera Quartus II v.11.0
Contextual Info: 5. DC & Switching Characteristics SII51005-4.5 Operating Conditions Stratix II devices are offered in both commercial and industrial grades. Industrial devices are offered in -4 speed grades and commercial devices are offered in -3 fastest , -4, -5 speed grades.

respack 8

Abstract: drawn pin configuration of ic 7408 drawn pin out configuration of ic 7408 Oupiin 0603 104P CONNECTOR, 32P FREEDM-32P672 M66EN PM2352 PM7380
Contextual Info: PM2352 FREEDM -32P672 PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1 DEVELOPMENT KIT BOARD PM7380 FREEDM -32P672 DEVELOPMENT KIT BOARD DESIGN DOCUMENT ISSUE 1: DECEMBER 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

SE370C712A

Abstract: digital clock notes C702 C722 SE370C702 TMS370 TMS370C002A TMS370C012A TMS370C302A TMS370C702
Contextual Info: Chapter 18 Electrical Specifications and Timings This chapter contains electrical and tinning information for the TMS370 family devices. This information is presented according to device category. Topic Page 18.1 Timing Parameter S y m b o ls . 18-2

EP2S30

Abstract: EP2S60 EP2S90 EP2S15 EP2S180 I747 verilog code fo fft algorithm 16 bit Array multiplier code in VERILOG TI 783
Contextual Info: Section I. Stratix II Device Family Data Sheet This section provides the data sheet specifications for Stratix II devices. This section contains feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC

T M 2313

Abstract: class 10 up board Datasheet 2012 verilog code pipeline ripple carry adder vhdl code for FFT 32 point EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 T432
Contextual Info: Section I. Stratix II Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix II devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information,

bst 1046

Abstract: Datasheet Library 1979 S 1854 8 bit Array multiplier code in VERILOG class 10 up board Datasheet 2012 CMOS applications handbook sensor 3414 vhdl code for FFT 32 point EP2S15 EP2S180
Contextual Info: Section I. Stratix II Device Family Data Sheet This section provides the data sheet specifications for Stratix II devices. This section contains feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC

QDR pcb layout

Abstract: verilog code fo fft algorithm
Contextual Info: Stratix II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SII5V1-4.5 Copyright 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

1553 VHDL

Abstract: class 10 up board Datasheet 2012 PS 229 T M 2313 SII5V1-2 CMOS applications handbook T 2109 verilog code pipeline ripple carry adder vhdl code for FFT 32 point EP2S15
Contextual Info: Stratix II Device Handbook, Volume 1 Preliminary Information 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com SII5V1-2.1 Copyright 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

TMS370C002A

Abstract: SE370C712A TMS370Cxxx C702 C722 SE370C702 TMS370 TMS370C012A TMS370C302A TMS370C702
Contextual Info: Chapter 18 Electrical Specifications and Timings This chapter contains electrical and tinning information for the TMS370 family devices. This information is presented according to device category. Topic Page 18.1 Timing Parameter S y m b o ls . 18-2

General Electric Semiconductor Data Handbook

Abstract: D 1609 VO A1 Datasheet Library 1979 S 1854 bst 1046 class 10 up board Datasheet 2012 CMOS applications handbook d 1878 DATA SHEET sensor 3414 toggle switches 2041 BY
Contextual Info: Stratix II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SII5V1-4.4 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

EP2S15

Abstract: EP2S180 EP2S30 EP2S60 EP2S90 A 27631 transistor
Contextual Info: Section I. Stratix II Device Family Data Sheet This section provides the data sheet specifications for Stratix II devices. This section contains feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC

Contextual Info: Section I. Stratix II Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix II devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information,

TMS370C777A

Abstract: SE370C712A TMS370C756A SE370C756A TMS370C712A SE370C712B SE370C777A SE370C758A
Contextual Info: Chapter 18 Electrical Specifications and Timings This chapter contains electrical and tinning information for the TMS370 family devices. This information is presented according to device category. Topic Page 18.1 Timing Parameter S y m b o ls .18-2

EP2S60F

Abstract: OV 5642 27631 VHDL fpga stratix II ep2s180
Contextual Info: Section I. Stratix II Device Family Data Sheet This section provides the data sheet specifications for Stratix II devices. This section contains feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC

OFWG*3203

Abstract: OFWG colour tv power supply bu 1802 chn 719 TRANSISTOR NPN D313 TDA3654 equivalent R1413 TDA2653 colour tv power supply circuit diagram TDA2578
Contextual Info: Philips Semiconductors Semiconductors for Television and Video Systems Contents PART A page SELECTION GUIDE Functional index 5 Numerical index 17 Maintenance list 27 GENERAL Quality 31 Pro Electron type numbering system for Discrete Semiconductors 31 Pro Electron type numbering system for Integrated Circuits

8 bit Array multiplier code in VERILOG

Contextual Info: Stratix II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SII5V1-4.1 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

Contextual Info: Stratix II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SII5V1-4.2 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

Contextual Info: SM470R1B1M-HT www.ti.com SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012 16/32-BIT RISC FLASH MICROCONTROLLER FEATURES 1 • • 2 • • • • • • High-Performance Static CMOS Technology SM470R1x 16/32-Bit RISC Core ARM7TDMI – 60-MHz System Clock (Pipeline Mode)

TC1107

Abstract: TC1108 TC1186
Contextual Info: ¡eluom Semiconductor, Inc. TC 1186 150mA CMOS LDO W ITH SHUTDO W N AND ERROR OUTPUT FEATURES G EN ER AL DESCRIPTION • ■ ■ ■ ■ ■ ■ The TC 1186 is a high accuracy typically ±0.5% CMOS upgrade for older (bipolar) low dropout regulators. De­