TAP ME Search Results

Contextual Info: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL • Single: FECL • Triple: MECL Electrical Specifications at 25OC Tap Delay Tolerances +/- 5% or 1.5ns +/- 0.8ns <10ns 10K ECL 5 Tap P/N Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 DECL-6 2.0 3.0 4.0 5.0

Contextual Info: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL • Single: FECL • Electrical Specifications at 25°C Electrical Specifications at 25°C Tap Delay Tolerances +/- 5% or 1,5ns +/- 0.8ns <10ns 10K ECL 5 Tap P/N Tap 1 Triple: MECL Tap 2 Tap 3 Tap 4

DS1010

Abstract: 74LS DS1010-100 DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010S dip switch data
Contextual Info: DS 1010 DALLAS DS1010 10-Tap Silicon Delay Line s e m ic o n d u c t o r FEATURES PIN ASSIGNMENT • All-silicon tim e delay ini r 1 14 V cc NO 2 13 TAP 1 TAP 2 [_ 3 12 TAP 3 4 11 TAP 5 TAP 6 \_ 5 10 TAP 7 TAP 4 6 9 TAP 9 TAP 6 • 10 taps equally spaced • Delays are stable and precise

74F04

Abstract: DS1004 DS1004M DS1004Z
Contextual Info: DS1004 DS1004 5-Tap High–Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All–silicon timing circuit • Five equally delayed clock phases per input IN 1 8 Vcc TAP 2 2 7 TAP 1 • Precise tap–to–tap delay tolerances of TAP 4 3 6 TAP 3 GND 4 5 TAP 5

XAITD

Abstract: XAITD-12 XAITD-15 XAITD-20 XAITD-25 XAITD-30 XAITD-35 XAITD-40 XAITD-50 XAITD-60
Contextual Info: XAITD Series FAST / TTL Buffered 10-Tap Delay Modules Low Profile 14-Pin Package Two Surface Mount Versions FAST/TTL Logic Buffered Electrical Specifications at 25OC FAST 10 Tap 14-Pin P/N Tap Delay Tolerances +/- 5% or 2ns +/- 1ns <15ns Tap 1 Tap 2 Tap 3

74ls gate symbols

Abstract: 74FO4 pin diagram of 74LS "Delay Lines" 74ls series 74LS SERIES cmos logic data DS1010-60 74LS series datasheet 74ls series logic DS1010-200
Contextual Info: DS1010 DS1010 10-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN1 1 14 VCC NC 2 13 TAP 1 IN 1 16 VCC TAP 2 3 12 TAP 3 NC 2 15 NC • Leading and trailing edge accuracy TAP 4 4 11 NC TAP 2 3 14 TAP 5 TAP 1 • Delay tolerance ±5% or ±2 ns, whichever is greater

50A10250

Abstract: 50A10750 50A-10151 50A-10250 218C 300C 50A-10101 50A-10201 50A-10251 50A-10500
Contextual Info: DUAL - IN - LINE PACKAGE TOP VIEW □ Schottky TTL compatible □ 10 equally spaced taps □ 14 pin package □ Low profile □ TTL compatible □ Auto insert or surface mount package styles Vcc 14 IN TAP 1 13 TAP 3 12 TAP 5 TAP 7 TAP 9 11 10 9 OUT 8 TAP 2

50A-10500

Abstract: 50A-10201 50A-10250 50A-10101 218C 300C 50A-10151 50A-10251 50A-10750 50A10250
Contextual Info: DIGITAL DELAY MODULES 50A, 52A, 52S Series 10 Tap 14 Pin Moulded DIP DUAL - IN - LINE PACKAGE TOP VIEW □ Schottky TTL compatible □ 10 equally spaced taps □ 14 pin package Vcc 14 TAP 1 13 TAP 3 12 TAP 5 11 w TAP 7 10 TAP 9 9 OUT 8 rpns~iirq^nr" Tnq-rrj^rT1

Contextual Info: T a p Bypass Jumper The Gilbert Tap Bypass Jumper is designed to maintain power and RF integrity through a tap housing when the normal circuit is interrupted by removing the tap face plate. The contact probe is spring loaded axially to accommodate a wide range of tap seizure mechanisms and

GIC-KSMP-KSMP-36

Contextual Info: Tap Bypass Jumper The Corning Gilbert Tap Bypass Jumper is designed to maintain power and RF integrity through a tap housing when the normal circuit is interrupted by removing the tap face plate. The contact probe is spring loaded axially to accommodate a wide range of tap seizure

74ls series

Abstract: DS1000Z "Delay Lines" TTL 74LS 00 TTL pin 74LS 00 74F04 74LS DS1000 DS1000M
Contextual Info: DS1000 DS1000 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • 5 taps equally spaced IN 1 14 Vcc NC 2 13 NC • Delays are stable and precise NC 3 12 TAP 1 TAP 2 4 11 NC NC 5 10 TAP 3 TAP 4 6 9 NC GND 7 8 TAP 5 • Both leading and trailing edge accuracy

RCD Components

Abstract: A0805 A1405 A1410 MIL-D-83532 SA0805
Contextual Info: ACTIVE DIGITAL DELAY LINES RESISTORS "CAPS & COILS "DELAY LINES A0805 SERIES 5-TAP 8-PIN DIP SA0805 SERIES 5-TAP 8-PIN SIP A1405 SERIES 5-TAP 8-PIN DIP A1410 SERIES 10-TAP 14-PIN DIP Wide selection of sizes! RCD’s digital delay lines have been designed to provide precise tap

TEC3020

Contextual Info: ^High-Speed RISC Delay Modules RISC Delay Module TEC3016 TEC3020 TEC3025 TEC3033 TEC3040 Tap Delay ns Tap Delay (ns) Tap Delay (ns) Tap Delay (ns) Tap Delay (ns) T„0=REF. T„0=REF. To0=R EF t do = ref . t do = ref . To1 = 6 .0 ± .4 5 Td1 = 6 . 0 ± .45

Contextual Info: SURFACE MOUNT ACTIVE DIGITAL DELAY LINES RESISTORS wCAPS & COILS wDELAY LINES SMA1405 SERIES - SMALL OUTLINE 5-TAP SMA2805 SERIES - PLCC PACKAGE 5-TAP SMA2810 SERIES - PLCC PACKAGE 10-TAP FEATURES r Non-standard delay times or tolerances r Non-symmetrical tap delays

PIN photodiode 510 nm

Abstract: fast photodiode amplifier Power Monitoring td 1410 SMF-28 optical fiber sensitivity dB photodiode pin optical fiber pm photodiode 1490 nm in line amplifier fiber
Contextual Info: Components Tap/Detector Optical insertion loss DiCon’s Tap/Detector is a hybrid component that combines the ultra flat spectral response of a thin film tap with a high sensitivity PIN photodiode for power monitoring applications. Hybrid Tap/Detectors minimize integration costs and module

PA19355

Abstract: ADVANCED COMMUNICATION DEVICES Silicon Power Corporation substation design
Contextual Info: SSLTC Solid State Load Tap Changer Product Applications Reliable Environmentally Sensible Low Maintenance Silicon Power SSLTC™ successfully addresses the reliability and maintenance issues of legacy load-tap changers of substation transformers. Legacy load-tap changers utilize electro-mechanical technology that includes numerous

Contextual Info: USB TAP Probe Users Guide Document Number: UTAPUG Rev 10.x, 9/2013 USB TAP Probe Users Guide, Rev. 10.x, 9/2013 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1 Introducing the CodeWarrior USB TAP Probe 1.1 What is the USB TAP

001H

Abstract: HSP43168 LF43168
Contextual Info: LF43168 LF43168 DEVICES INCORPORATED Dual 8-Tap FIR Filter Dual 8-Tap FIR Filter DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 66 MHz Data and Computation Rate ❑ Two Independent 8-Tap or Single 16-Tap FIR Filters ❑ 10-bit Data and Coefficient Inputs ❑ 32 Programmable Coefficient Sets

Contextual Info: DS1004 5-Tap High Speed Silicon Delay Line www.dalsemi.com PIN ASSIGNMENT FEATURES All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances of ±1.5 ns

Contextual Info: D S 1005 DALLAS SEMICONDUCTOR FEATURES DS1005 5-Tap Silicon Delay Line PIN ASSIGNMENT • All-silicon time delay • 5 taps equally spaced Vcc IN □ 1 16 □ Vcc NC NC □ 2 15 □ NC 3 14 4 13 □ TAP 1 5 12 6 7 11 □ TAP 3 10 □ NC 8 9 □ TAP 5 E TAP 2 E

Contextual Info: DS1004 5-Tap High Speed Silicon Delay Line www.dalsemi.com FEATURES PIN ASSIGNMENT All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances of ±1.5 ns

MC68EC030 opcode

Abstract: 27F020 ci str 9656 MC68EC030 27C010 MC68340 MC68360 SCR BRX 49 PIN MCM36100S 156 35K 301
Contextual Info: SECTION 8 SCAN CHAIN TEST ACCESS PORT The QUICC provides a dedicated user-accessible test access port TAP that is JTAG compatible. The QUICC TAP contains one additional signal not available with the MC68340 TAP—the test reset (TRST) signal. This signal provides an asynchronous reset to the TAP.

Contextual Info: THE DOWNTIME ELIMINATOR: WET TAP VALVE ASSEMBLIES Sensor Restraining System Model FP-319 Wet Tap Assembly $ 453 MADE IN USA Shown Smaller Than Actual Size Wet Tap Valve You can completely eliminate downtime resulting from flow sensor maintenance with the simple addition of OMEGA’s FP-319 Wet Tap Valve

Contextual Info: 16 Pin DIL 5 Tap 10K ECL Compatible Active Delay Lines TAP 1 nS ±5% TAP 2 nS ±5% 3.0 TY P f 3.0 TYP-f 3.0 TYP 4 ± 1.0 5 ± 1.0 6 ± 1.0 8 ± 1.0 10±1.0 15± 1.5 20 ±2.0 30 ± 2.0 40 50 60 70 80 90 100 120 140 160 180 200 TAP 3 nS ±5% TAP 4 nS±5% OUTPUT