TAP ME Search Results

Contextual Info: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL Single: FECL Triple: MECL * * Electrical Specifications at 25°C_ 10K ECL 5 Tap P/N Tap Delay Tolerances +/- 5% or 1.5ns +/- 0.8ns <10ns Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5

Contextual Info: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL • Single: FECL • Triple: MECL Electrical Specifications at 25OC Tap Delay Tolerances +/- 5% or 1.5ns +/- 0.8ns <10ns 10K ECL 5 Tap P/N Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 DECL-6 2.0 3.0 4.0 5.0

Contextual Info: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL • Single: FECL • Electrical Specifications at 25°C Electrical Specifications at 25°C Tap Delay Tolerances +/- 5% or 1,5ns +/- 0.8ns <10ns 10K ECL 5 Tap P/N Tap 1 Triple: MECL Tap 2 Tap 3 Tap 4

Contextual Info: DS 1010 DS1010 DALLAS SEMICONDUCTOR 10-Tap Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay IN1 [ " ^3 7 ] vcc • 10 taps equally spaced • Delays are stable and precise NC c ] TAP 1 TAP 2 C ] TAP 3 ] TAP 5 ] TAP 7 TAP 4 C 1 TAP 9 TAP 6 d

SMD ACDM

Abstract: ACDM ACDM-30 ACDM-35 ACDM-40 ACDM-50 ACDM-60
Contextual Info: ACDM Series Advanced CMOS Logic Buffered 5-Tap Delay Modules 74ACT type input is compatible with TTL Electrical Specifications at 25OC Tap Delay Tolerances +/- 5% or 2ns +/- 1ns <13ns 74ACT 5 Tap 14-pin DIP P/N Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 Low Profile 14-Pin Package

DS1010

Abstract: 74LS DS1010-100 DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010S dip switch data
Contextual Info: DS 1010 DALLAS DS1010 10-Tap Silicon Delay Line s e m ic o n d u c t o r FEATURES PIN ASSIGNMENT • All-silicon tim e delay ini r 1 14 V cc NO 2 13 TAP 1 TAP 2 [_ 3 12 TAP 3 4 11 TAP 5 TAP 6 \_ 5 10 TAP 7 TAP 4 6 9 TAP 9 TAP 6 • 10 taps equally spaced • Delays are stable and precise

AIDM

Abstract: AIDM-11 AIDM-13 AIDM-15 AIDM-20 AIDM-25 AIDM-30 AIDM-35 AIDM-40 AIDM-50
Contextual Info: AIDM Series FAST / TTL Buffered 5-Tap Delay Modules Electrical Specifications at 25OC Tap Delay Tolerances +/- 5% or 2ns +/- 1ns <13ns FAST/TTL 14-Pin DIP P/N Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 Low Profile 14-Pin Package Two Surface Mount Versions FAST/TTL Logic Buffered

74F04

Abstract: DS1004 DS1004M DS1004Z
Contextual Info: DS1004 DS1004 5-Tap High–Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All–silicon timing circuit • Five equally delayed clock phases per input IN 1 8 Vcc TAP 2 2 7 TAP 1 • Precise tap–to–tap delay tolerances of TAP 4 3 6 TAP 3 GND 4 5 TAP 5

74F04

Abstract: DS1004 DS1004M DS1004Z
Contextual Info: DS1004 DS1004 5-Tap High–Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All–silicon timing circuit • Five equally delayed clock phases per input IN 1 8 Vcc TAP 2 2 7 TAP 1 • Precise tap–to–tap delay tolerances of TAP 4 3 6 TAP 3 GND 4 5 TAP 5

XAITD

Abstract: XAITD-12 XAITD-15 XAITD-20 XAITD-25 XAITD-30 XAITD-35 XAITD-40 XAITD-50 XAITD-60
Contextual Info: XAITD Series FAST / TTL Buffered 10-Tap Delay Modules Low Profile 14-Pin Package Two Surface Mount Versions FAST/TTL Logic Buffered Electrical Specifications at 25OC FAST 10 Tap 14-Pin P/N Tap Delay Tolerances +/- 5% or 2ns +/- 1ns <15ns Tap 1 Tap 2 Tap 3

74ls gate symbols

Abstract: 74FO4 pin diagram of 74LS "Delay Lines" 74ls series 74LS SERIES cmos logic data DS1010-60 74LS series datasheet 74ls series logic DS1010-200
Contextual Info: DS1010 DS1010 10-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN1 1 14 VCC NC 2 13 TAP 1 IN 1 16 VCC TAP 2 3 12 TAP 3 NC 2 15 NC • Leading and trailing edge accuracy TAP 4 4 11 NC TAP 2 3 14 TAP 5 TAP 1 • Delay tolerance ±5% or ±2 ns, whichever is greater

74LS

Abstract: DS1010 DS1010-100 DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010S ds1010-500
Contextual Info: DS1010 DS1010 10-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN1 1 14 VCC NC 2 13 TAP 1 IN 1 16 VCC TAP 2 3 12 TAP 3 NC 2 15 NC • Leading and trailing edge accuracy TAP 4 4 11 NC TAP 2 3 14 TAP 5 TAP 1 • Delay tolerance ±5% or ±2 ns, whichever is greater

11ACB50012E

Abstract: 11acb10012e 11ACB50112E 14 PIN DIL PACKAGE 11ACB10112E 11ACB20012E 11acb25112e DIL package 11ACB 300C
Contextual Info: DELAY LINESHASeries 10 Tap 14 pin DIL Package STANDARD PIN-OUT CODE E • Lumped constant • Low profile GND 14 OUT TAP 9 TAP 8 TAP 7 TAP 6 TAP 5 8 O TTL and DTL compatible • Low distortion and low attenuation • High reliability • Auto insertable

Contextual Info: Tap/Isolator Hybrid Tap - Isolator Hybrid Single Stage Dual Stage 1535 nm – 1565 nm 1530 nm – 1570 nm ≤ 0.7 dB ≤ 0.9 dB Parameter Wavelength Range Insertion Loss in Signal Channel for 1% tap ratio Insertion Loss in Tap Channel ≤ 14dB (5% Tap), ≤ 20.8 dB (1% Tap)

50A10250

Abstract: 50A10750 50A-10151 50A-10250 218C 300C 50A-10101 50A-10201 50A-10251 50A-10500
Contextual Info: DUAL - IN - LINE PACKAGE TOP VIEW □ Schottky TTL compatible □ 10 equally spaced taps □ 14 pin package □ Low profile □ TTL compatible □ Auto insert or surface mount package styles Vcc 14 IN TAP 1 13 TAP 3 12 TAP 5 TAP 7 TAP 9 11 10 9 OUT 8 TAP 2

Contextual Info: HYBRID Tap - Isolator Hybrid Tap – Tap Isolator HybridHybrid – Isolator Tap – Isolator Hybrid Features: Features Features Tap – Isolator Features lossinsertion and PDL •Ultra-low insertion loss and PDL •Ultra-low •High isolation insertion loss and PDL

VOA MEMS

Abstract: VOA dicon dicon
Contextual Info: MEMS Tap/VOA Hybrid DiCon's MEMS Tap/VOA Hybrid is based on a micro-electromechanical system MEMS chip integrated with a thin film filter. The thin film tap filter couples a portion of the input signal to an output tap fiber while transmitting the rest of the input signal

50A-10500

Abstract: 50A-10201 50A-10250 50A-10101 218C 300C 50A-10151 50A-10251 50A-10750 50A10250
Contextual Info: DIGITAL DELAY MODULES 50A, 52A, 52S Series 10 Tap 14 Pin Moulded DIP DUAL - IN - LINE PACKAGE TOP VIEW □ Schottky TTL compatible □ 10 equally spaced taps □ 14 pin package Vcc 14 TAP 1 13 TAP 3 12 TAP 5 11 w TAP 7 10 TAP 9 9 OUT 8 rpns~iirq^nr" Tnq-rrj^rT1

50A52

Contextual Info: DIGITAL DELAY MODULES 5QA, 52A, 52S Series 10 Tap 14 Pin Moulded DIP DUAL - IN - LINE PACKAGE TOP VIEW □ Schottky TTL compatible □ 10 equally spaced taps □ 14 pin package Vcc 14 TAP 1 13 TAP 3 12 TAP 5 11 TAP 7 10 TAP 9 9 OUT 8 □ Low profile □ TTL compatible

Contextual Info: T a p Bypass Jumper The Gilbert Tap Bypass Jumper is designed to maintain power and RF integrity through a tap housing when the normal circuit is interrupted by removing the tap face plate. The contact probe is spring loaded axially to accommodate a wide range of tap seizure mechanisms and

GIC-KSMP-KSMP-36

Contextual Info: Tap Bypass Jumper The Corning Gilbert Tap Bypass Jumper is designed to maintain power and RF integrity through a tap housing when the normal circuit is interrupted by removing the tap face plate. The contact probe is spring loaded axially to accommodate a wide range of tap seizure

74ls series

Abstract: DS1000Z "Delay Lines" TTL 74LS 00 TTL pin 74LS 00 74F04 74LS DS1000 DS1000M
Contextual Info: DS1000 DS1000 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • 5 taps equally spaced IN 1 14 Vcc NC 2 13 NC • Delays are stable and precise NC 3 12 TAP 1 TAP 2 4 11 NC NC 5 10 TAP 3 TAP 4 6 9 NC GND 7 8 TAP 5 • Both leading and trailing edge accuracy

Contextual Info: T a p Bypass Jumper v The Gilbert Tap Bypass Jumper is designed to maintain power and RF integrity through a tap housing when the normal circuit is interrupted by removing the tap face plate. The contact probe is spring loaded axially to accommodate a wide range of tap seizure mechanisms and

74F04

Abstract: 74LS DS1000 DS1000M DS1000Z
Contextual Info: DS1000 DS1000 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • 5 taps equally spaced IN 1 14 Vcc NC 2 13 NC • Delays are stable and precise NC 3 12 TAP 1 TAP 2 4 11 NC NC 5 10 TAP 3 TAP 4 6 9 NC GND 7 8 TAP 5 • Both leading and trailing edge accuracy