T 5.5 W Search Results

Contextual Info: CONFIDENTIAL TABLE 1.1, ABSOLUTE MAXIMUM RATINGS O p e ra tin g T e m p e ra tu re Range -4 0 t o +85 d e g re e s C S to ra g e T e m p e ra tu re Range -5 5 to +100 d e g re e s C V c c V o lta g e , V d c +5.5 V tu n e V o lta g e , V d c +5.5 DC V o lta g e applied t o

Contextual Info: T O SH IB A TA6009FN TO SH IBA BIPO LAR LINEAR INTEGRATED CIRCUIT SILICON M ONOLITHIC TA6009FN SHOCK SENSOR IC Ich VERSION TA6009FN detects an existence o f external shock through t h p <;hnrk i p n i n r a n d n i i t n u t FEATURES • TA6009FN operates from 2.7 ~5.5 V DC single power

Contextual Info: SN74LV8151 10ĆBIT UNIVERSAL SCHMITTĆTRIGGER BUFFER WITH 3ĆSTATE OUTPUTS SCES610 − OCTOBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 15 ns at 5 V D Schmitt-Trigger Inputs Allow for Slow Input D D D D D D D NT OR PW PACKAGE TOP VIEW T/C A B D1 D2

Contextual Info: SILICON NPN TRIPLE DIFFUSED MESA TYPE 2SC5129 U nit in mm HORIZO NTAL DEFLECTION O U TPU T FOR HIGH RESOLUTION DISPLAY, COLOR TV. 1 5.5 ± 0.5 a 3.6 ±0.3 • • • • - 3 ^ - - .1- HIGH SPEED SW ITCHING APPLICATIONS. 3 0±0.3 H igh Speed : tf= 0.15/js Typ.

UP-850

Contextual Info: CONFIDENTIAL TABLE 1.1, ABSOLUTE MAXIMUM RATINGS O p e ra tin g T e m p e ra tu re Range -4 0 t o +85 d e g re e s C S to r a g e T e m p e ra tu re Range -5 5 to +100 d e g re e s C V c c V o lta g e , V d c +5.5 V tu n e V o lta g e , V d c +18.0 DC V o lta g e applied t o

5252 F ic

Contextual Info: TOSHIBA July 1997 TIM1414-5-252 1. R F PERFO R M A N CE SP E C IFIC A T IO N S CHARACTERISTICS SYMBOL Output Power at ldB Compression Point P i dB Power Gain at ldB Compression Point GldB CONDITION MIN. TYP. MAX. UNIT 36.5 37.5 — dBm 4.5 5.5 — dB - 2.0

Contextual Info: CONFIDENTIAL TABLE 1,1, ABSOLUTE MAXIMUM RATINGS O p e ra tin g T e m p e r a tu r e S to r a g e V cc T e m p e r a tu r e R ange -4 0 t o + 85 d e g r e e s C -5 5 +100 d e g r e e s C to +5.5 V o lta g e , V d c V tu n e V o lta g e , V d c DC V o lt a g e

SN74LVCC4245

Contextual Info: SN74LVCC4245 OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS _ SCAS584A - NOVEMBER 1696 - REVISED JANUARY 1997 EPICrM Enhanced-Performance Implanted CMOS Submicron Process DB, DW, OR PW PACKAGE

Contextual Info: TC74HCT563AP/AF TC74HCT573AP/AF/AFW O C T A L D - T Y P E L A T C H WI TH 3 - S T A T E O U T P U T TC74HCT683AP/AF INVERTING TC74HCT673AP/AF/AFW N O N -IN V E R T IN G The TC74HCTS63A and TC74HCT573A are high speed CMOS OCTAL LATCH with 3 -S T A T E O UTPUT

sn74als662

Abstract: sn74als663 sn74als662a SN74ALS853 2114D
Contextual Info: SN54ALS652, SN54A LS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SDAS066E - DECEMBER 1983 - REVISED JANUARY 1995 Bus Transceivers/Registers Independent Registers and Enables for

Contextual Info: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW

SN54HCT240

Abstract: 8S63
Contextual Info: SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS _ SCLS174A - MARCH 1984 - REVISED JANUARY 1996 • Inputs Are TTL-Voltage Compatible • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • SN54HCT240 . . . J OR W PACKAGE

Contextual Info: TC74HCT240AP/AF/AFW TC74HCT241AP/AF/AFW TC74HCT244AP/AF/AFW O C T A L BU S B U F F E R W ITH TC74HCT240 A P / A F / A F W TC 74H C T241A P /A F/ AFW TC 74 H C T2 44 A P /A F/A FW II T T L IN P U T L E V E L IN V E R T E D ,3 - S T A T E O U T P U T S NON-IN V E R T E D ,3 - S T A T E O U TP U TS

74AC11520

Contextual Info: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations

Contextual Info: SN54HCT125, SN74HCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS069S- NOVEMBER 198« - REVISED MARCH 1996 • ■ I • • Inputs Are TTL-Voltage Compatible High-Current 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers I I •

Contextual Info: SN54HCT652, SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS _S C L S 1 7 9 A - MARCH 1 9 6 4 - REVISED JANUARY 1906 • Inputs Are TTL-Voltage Compatible • Independent Registers and Enables for A and B Buses •

Contextual Info: SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS174A - MARCH 1984 - REVISED JANUARY 1996 Inputs Are TTL-Voltage Compatible SN54HCT240. . . J OR W PACKAGE SN74HCT240 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer

TI009

Contextual Info: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

Contextual Info: TEXAS INSTR 0=^1723 oaaBü? 1 5SE D LOGIC SN54ALS131, SNB4AS131A, SN74ALS131, SN74AS131A 3-LINE TO 8-LINE DECODERSIDEMULTIPLEXERS WITH ADDRESS REGISTERS r-<U.-2('55 D 2 6 6 1 , A PRIL 1 9 8 2 - R E V IS E D M AY 1986 SN54ALS131, SN54AS131A . . . J PACKAGE

D3402

Abstract: 74ACT16245
Contextual Info: 54ACT16245, 74ACT16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0182— D3402, DECEMBER 1989— REVISED MARCH 1990 54ACT16245 . . . WD PACKAGE 74ACT16245 . . . DL PACKAGE Members of the Texas Instruments Widebus Family TOP VIEW Packaged in Shrink Small Outline 300-mil

D2957

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11853, 74AC 11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS TI0157— D3473, MARCH 1990 54AC11B53 . . . JT PACKAGE 74AC11853 . . . DW OR NT PACKAGE High-Speed Bus Transceivers with Parity Generator/Checker TOP VIEW Parity Error Flag Open-Drain Output • Register for Storage of the Parity Error Flag

F251B

Abstract: DFS06
Contextual Info: SN54F251B, SN74F251B 1-0F-8 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SDFS066A - MARCH 1987 - R EVISED O CTO BER 1993 3-State Versions of SN54F151B and SN74F151B 3-State Outputs Interface Directly With System Bus Performs Parallel-to-Serial Conversion

Contextual Info: 54AC11377, 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE TI0180— D3420, M A R C H 1990 Contains Eight D-Type Flip-Flops 54AC11377 . . . JT PACKAGE 74AC11377 . . . DW OR NT PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW 1Q [ 2Q [ 3Q [