SYNCHRONOUS ADDRESS MULTIPLEXER Search Results

Contextual Info: • MARCH 1990 PXÆ SSEY ADVANCED INFORMATION SEMICONDUCTORS PDSP16520 QUAD - PORT SYNCHRONOUS RAM Supersedes September 1989 edition The PDSP16520 contains 1K x 16 bits of Dual-Port Static RAM with separate read and write address ports. All memory and I/O operations are synchronous to a user supplied system

UT16MX110

Abstract: SMD S6
Contextual Info: Standard Products UT16MX113/114/115 Analog Multiplexer Preliminary Data Sheet August 24, 2011 FEATURES            16-to-1 Analog Mux 100Signal paths typical 5V single analog supply Rail-to-Rail signal handling Asynchronous RESET input

Contextual Info: Standard Products UT16MX110/111/112 Analog Multiplexer Preliminary Data Sheet January 24, 2012 FEATURES INTRODUCTION       The UT16MX110/111/112 are low voltage analog multiplexers with a convenient LVCMOS 3.3V digital interface. The analog muxes have Break-Before-Make architecture with a low

Contextual Info: Mixed-Signal Products UT16MX113/114/115 Analog Multiplexer Preliminary Data Sheet July 15, 2011 FEATURES            16-to-1 Analog Mux 100Signal paths typical 5V single analog supply Rail-to-Rail signal handling Asynchronous RESET input

446H

Abstract: 272M 299M 352M GO1555 GS1582 GS1582-IBE3 804h-807h Audio Multiplexer vanc
Contextual Info: GS1582 Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleanerTM Key Features • HD-SDI, SD-SDI, DVB-ASI transmitter with audio embedding • Integrated SMPTE 292M and 259M-C compliant cable driver • Integrated ClockCleaner • User selectable video processing features, including:

AL4CX3650

Abstract: AL4CX3660 AL4CX3670 AL4CX3680 AL4CX3690
Contextual Info: AL4CX3650/AL4CX3660/ AL4CX3670/AL4CX3680/AL4CX3690 2K/ 4K/ 8K/ 16K/ 32K x 36 Synchronous FIFOs Applications - ATM switches Routers Cable modems Wireless base stations SONET Synchronous Optical Network multiplexers Multimedia systems TBC(Time Base Corrector)

Contextual Info: MX844 12 Bit, Multi-Channel Power & Temp Sensor For Monitor & Control Systems Features Description • Wide Input Supply Range: 4.5V to 40V • Programmable Gain Differential Amplifier ±10mV, ±25mV, ±50mV, ±250mV Ranges • 4 Channel Differential Input Multiplexer

LTC1095

Abstract: LTC1095BMJ LTC1095CCN LTC1095CCJ LTC1095BCJ GAIA Converter motorola TYA LTCI095S 2N3906V TMS70C02
Contextual Info: uim LTC1095 Complete 10-Bit Data Acquisition System with On Board Reference FECHNOLOGY F€ATUR€S DCSCRIPTIOn • On Board 5V Precision Buried Zener Reference ■ Software Controlled 6 Channel Multiplexer ■ Differential and Single Ended Input Capability

FIFOs FIFO Memory

Abstract: AL4CE205 AL4CE215 AL4CE225 AL4CE235 AL4CE245
Contextual Info: AL4CE205/215/225/235/245 256, 512, 1K, 2K, 4K x 18 Advanced Synchronous FIFOs Features Applications - • Multimedia System ATM Switches Routers Cable Modems Wireless Base Stations SONET Synchronous Optical Network Multiplexers TBC(Time Base Corrector) Hard Disk cache memory

AL4CS215

Abstract: AL4CS225 AL4CS235 AL4CS245 AL4CS205
Contextual Info: AL4CS205/215/225/235/245 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs Applications - Features Multimedia System ATM Switches Routers Cable Modems Wireless Base Stations SONET Synchronous Optical Network Multiplexers TBC(Time Base Corrector) Hard Disk cache memory

Contextual Info: Idt FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER IDT54/74FCT162H272AT/CT/ET Integrated Device Technology, Inc. FEATURES: multiplexers for use in synchronous memory interleaving applications. All registers have a common clock and use a clock enable CExxx) on each data register to control data

HD64572

Abstract: ADE-602-127A HD64572AFL33 intel 80386 block diagram 1S2074H TRB20 receiver eft 317 transistor TRB20 CDA 10.7 MC 40 Hitachi DSA00211
Contextual Info: HD64572 SCA-II User’s Manual ADE-602-127A Rev. 2.0 October 19, 1998 Hitachi, Ltd. MC-Setsu Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in

ic 4013

Abstract: CI 4013 CI 4013 BE pin diagram of ic 4013 c4013 IDT74ALVCH16276 SO56-2 PA 4013 CMOS 4013 4013 ic
Contextual Info: 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER IDT74ALVCH16276 ADVANCE INFORMATION Integrated Device Technology, Inc. bidirectional, 12-bit, registered, bus multiplexers for use in synchronous memory interleaving applications. All registers have a common clock and use a clock enable CExxx on

IS61QDB22M36

Abstract: D0-35 IS61QDB24M18
Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Two echo clocks (CQ and CQ) that are delivered

Contextual Info: 72 Mb 2M x 36 & 4M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . Advanced Information January 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

Contextual Info: 72 Mb 2M x 36 & 4M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . Advanced Information February 2008 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

IS61QDB22M18-250M3I

Abstract: D0-35 IDD401 IS61QDB21M36-300M3 IS61QDB21M36-300M3L IS61QDB21M36-250M3LI
Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 2) Synchronous SRAMs . I MAY 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with early write operation.

Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 2) Synchronous SRAMs . ISSI OCTOBER 2006 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations.

Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . Advanced Information January 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations.

IS61DDB41M36

Abstract: 61DDB42M18 IS61DDB42M18
Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 4) CIO Synchronous SRAMs . I JANUARY 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation.

Contextual Info: 72 Mb 2M x 36 & 4M x 18 7 DDR-II (Burst of 4) CIO Synchronous SRAMs D . I ADVANCED INFORMATION JANUARY 2008 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation.

3x36

Contextual Info: 72 Mb 2M x 36 & 4M x 18 7 DDR-II (Burst of 4) CIO Synchronous SRAMs D . I ADVANCED INFORMATION JANUARY 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation.

Full function 100Base-T Ethernet Media Access Controller MAC Compliant with IEEE 802.3u Specificati

Abstract: MAC110 MACTOP RPEF1 PCMCIA Fast Ethernet HRW-1
Contextual Info: Features • Full function 100Base-T Ethernet Media Access Controller MAC • Compliant with IEEE 802.3u Specification • Contents: • • • • – 10/100 Media Access Controller (MAC110) – 32-bit Statistic Module (STAT) – Station Address Logic (SAL)

RC28F256K18C120

Abstract: GE28F256K18C RC28F256K3C120 GE28F256K18C120 RC28F256K3C120 lead free flowchart of bluetooth technology RC28F128K18
Contextual Info: 3 Volt Synchronous Intel StrataFlash Memory 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 x16 Datasheet Product Features • Performance — 110/115/120 ns Initial Access Speed for 64/128/256 Mbit Densities — 25 ns Asynchronous Page-Mode Reads,