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UC3901 application diagrams

Abstract: UC2901 T270pF UC1901 scf 4242 UC3901
Contextual Info: y U N IT R O D E UC1901 UC2901 UC3901 Isolated Feedback Generator • Low-Cost Alternative to Optical Couplers • Internal 1% Reference and Error Amplifier • Internal Carrier Oscillator Usable to 5mHz • Modulator Synchronizable to an External Clock •

Contextual Info: TOSHIBA TC55V2325FF-100 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 65,536 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V2325FF is a 2 ,0 9 7 ,1 5 2 bit synchronous pipelined burst SRAM that is organized as 65,536 words by 32 bits and designed for use in a secondary cache to support MPUs which have burst

74LS169BN

Abstract: 74S169
Contextual Info: TYPES SN54LS169B, SN54S168, SN54S169, SN74LS169B, SN74S168, SN74S169 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS OCTOBER 1976 —REVISED MAY 1983 S168 . . . SYNCHRONOUS UP/DOW N DECADE COUNTERS 'LS169B, 'S169 . . . SYNCHRONOUS UP/DO W N BINARY COUNTERS SN 54S 168, 5N 54LS169B, S N 54S 169 . . . J OB W PACKAGE

i486

Contextual Info: SN74BCT2141 2-WAY 8K x 18 SYNCHRONOUS CACHE DATA RAM D3613. A UG UST 1990 2-Way 8K x 18 Bit Architecture FN PACKAGE TOP VIEW Synchronous Read and Write Access at 50 MHz Clock Frequency Incorporates Burst Counter for Burst-Read (Read-Hit) Cycles or Burst-Write (Line-Fill)

SBP9989

Contextual Info: TEXAS INSTR -CUC/UP} 2^ 8 9 6 17 22 TEXAS INSTR UC/UP DE j flTbl7H2 DDS1E3S 7 | I 29C 21235 T S 2 - 3 3 '0 3 D SBP9964 TIM IN G C O N T R O LLER FOR THE SBP9900A 1. IN TRO DU CTIO N KEY FEATURES • 1.2 14-Bit Interval Timer-Event Counter • R E S E T , H O L D , and L O A D synchronization

Contextual Info: a d v a n c e in fo r m a 7to/vUT54ACS 191/UT54ACTS191 Radiation-Hardened Synchronous 4-Bit Up-Down Counters FEATURES • Single dow n/up count control line • Look-ahead circuitry enhances speed of cascades counters • Fully synchronous in count inodes

sn74f160

Abstract: SN54F160
Contextual Info: SN 54F160A, SN 54F162A, SN 74F160A, SN 74F162A SYNCHRONOUS 4-BIT DECADE COUNTERS D2932, MARCH 1987-REVISED JANUARY 1989 • Internal Look-Ahead for Fast Counting • Carry O utput fo r n-Bit Cascading • Fully Synchronous Operation for Counting • Package Options Include Plastic "Sm all

P686

Contextual Info: TOSHIBA 1. TMP68652 INTRODUCTION The TM P68652 MPCC form ats, tran sm its, and receives synchronous se ria l d ata while supporting bit-oriented protocols BOP or byte-control protocols (BC P). The p a r a lle l b u s of the M PCC re a d ily in te r fa c e s w ith th e 6 8 0 0 an d T L C S -6 8 0 0 0

Contextual Info: SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTERS D2«»1, APRIL 1982 - REVISED OCTOBER 1988 Synchronous Load Direct Overriding Clear Parallel to Serial Conversion SN74ALS106 D O R N PACKAGE TOP VIEW U i 6 ] v Cc SE F » C Package Options Include Plastic 'Small

T0T7250

Abstract: FS1N
Contextual Info: TCD6162AU GEN ERAL The TC6162AU is a C M O S LSI chip for generating NTSC television synchronization signals and operating a 400,000- pixel FITCCD area image sensor. This chip covers the electronic shutter m ode of 1 /60 to 1 / 2000 seconds. It has a vertical reset pin that enables

TM4SN64EPN10

Abstract: TM2SN64EPN-10 TM48N64EPN TM4SN64EPN-10 TMS626812
Contextual Info: TM2SN64EPN 2097152 BY 64-BIT TM4SN64EPN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES _ SYNCHRONOUS CLOCK CYCLE TIME *CK3 , {CL = 3 t ACCESS TIME CLOCK TO OUTPUT >CK2 CL = 2) *CK3 (CL = 3) *CK2 (CL = 2) • • • • • • • •

cd018

Contextual Info: TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY _ SM JS633 - NOVEMBER 1997 PAF 80-PIN PACKAGE TOP VIEW 8 X to. > i> 5 ¡r lo o Ear IS IS IS |w lo I * 0017 C D018 C DQ19 C VDDE C VSSE C OQ20 C 0Q21 C 0Q22 C DQ23 C DQ24 C DQ25 C

Contextual Info: SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056A - D2932, MARCH 19B7-REVISED OCTOBER 1993 • Internal Look-Ahead Circuitry for Fast Counting • Carry Output for N-Bit Cascading D OR N PACKAGE TOP VIEW • Fully Synchronous Operation for Counting • Package Options Include Plastic

Contextual Info: TO SHIBA THMY644071EG-10 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 4,194,304-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY644071EG is a 4,194,304-word by 64-bit synchronous dynamic RAM module consisting of four TC59S6416FT DRAMs and an unbuffer on a printed circuit board.

center tapped transformer

Contextual Info: m b U NITRODE Design Note Inductorless Bias Supply Design for Synchronous Rectification and High Side Drive Applications by Bill Andreycak Developing a bias supply which is higher than a power supply’s input voltage is usually required in high side switch applications. Two such exam­

74278

Contextual Info: TYPES SN54278, SN74278 4-BIT CASCADABLE PRIORITY REGISTERS M AY 1 972 —R E V ISE D A P R IL 1 98 5 Latched Data Inputs Serve as Buffer Register and Can also: Synchronize Data Acquisition "Debounce" Mechanical Switch Input • Cascading Input PO and Output P1

SDFS089

Contextual Info: SN74F169 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER SDFS089 - MARCH 1987 - REVISED OCTOBER 1393 Fully Synchronous Operation for Counting and Programming d or n package <TOP v i e w Internal Look-Ahead Circuitry for Fast Counting U /D [ 1 C LK [ 2 Carry Output for N-Bit Cascading

74LS166A

Abstract: 54ls166a 54LS166
Contextual Info: SN54166, SN 54LS166A, SN74166. SN 74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS OCTOBER 1976 - REVISED MARCH 1988 S N 54166, S N 54LS 166A . . . J OR W PACKAGE S N 7416 6 . . . N PACKAGE S N 74LS 166A . . . D OR N PACKAGE • Synchronous Load • Direct Overriding Clear

um611864

Contextual Info: a S amar a a P R E L IM IN A R Y - UM611864 64K X 18 Bit Synchronous High Speed CMOS SRAM Features Single +5V power supply Fast access times: 9/11 ns Current: Operating: 275mA Standby: 95mA Synchronous self-timed write Individual byte write control synchronous output enable

SN54ALS192

Abstract: 74ALS192
Contextual Info: SN54ALS192, SN54ALS193, SN74ALS192. SN74ALS193 SYNCHRONOUS 4 BIT UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR D 2 6 6 1 , D EC EM BE R 1 9 8 2 - R E V IS E O M A Y • Look-A head C irc u itry Enhances Cascaded C ounters • Fully S ynchronou s in C o u n t M odes

Contextual Info: UT54ACS 169/UT54ACTS 169 Radiation-Hardened 4-Bit Up-Down Binary Counters FEATURES • • • • • • • • • • Fully synchronous operation for counting and programming Internal look-ahead for fast counting Carry output for n-bit cascading Fully independent clock circuit

SN54ALS568

Contextual Info: SN54ALS568A, SN54ALS569A, SN74ALS568A, SN74ALS569A SYNCHRONOUS 4-BIT UPjDOWN DECADE AND BINARY COUNTERS WITH 3 STATE OUTPUTS D 2 6 6 1 , APRIL 1 9 8 2 -R E V IS E D M A Y 1 9 8 6 • 3 -S ta te Q O u tp u ts D rive Bus Lines D irec tly • C o u n te r O p era tio n In d e p e n d e n t o f 3 -S ta te O u tp u t

Contextual Info: SM/SMJ34061 VIDEO SYSTEM CONTROLLER JULY 1 98 7 • Generates User-Programmable Control Signals Horizontal Sync, Vertical Sync, and Blanking Which Support a Broad Range of Raster-Scan Display Systems with Varying Resolutions and Scan Rates S M J 3 4 0 6 1 G B . . . 68-P IN PGA

LQFP-100

Contextual Info: TOSHIBA TC55WD1618FF-133,-150,-167 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT TENTATIVE SILICON GATE CMOS 1,048,576-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM DESCRIPTION The TC55WD1618FF is a synchronous static random access memory SRAM organized as 1,048,576 words by