STRATIX 3 Search Results

EP20K200E

Abstract: EP20K400E ALTMULT_ACCUM
Contextual Info: 3. Transitioning APEX Designs to Stratix & Stratix GX Devices S52012-3.0 Introduction Stratix and Stratix GX devices are Altera’s next-generation, system-ona-programmable-chip SOPC solution. Stratix and Stratix GX devices simplify the block-based design methodology and bridge the gap

types of multipliers

Abstract: types of binary multipliers algebraic clock cycles values binary multiplier binary numbers multiplication EP2S15 EP2S180 EP2S30 EP2S60 EP2S90
Contextual Info: Implementing Multipliers in FPGA Devices July 2004, ver. 3.0 Introduction Application Note 306 Stratix II, Stratix, Stratix GX, Cyclone II, and Cyclone devices have dedicated architectural features that make it easy to implement highperformance multipliers. Stratix II, Stratix, and Stratix GX devices feature

LHF16J06

Abstract: EPC16 0x00010040
Contextual Info: 2. Remote System Configuration with Stratix & Stratix GX Devices S52015-3.1 Introduction Altera Stratix® and Stratix GX devices are the first programmable logic devices PLDs featuring dedicated support for remote system configuration. Using remote system configuration, a Stratix or Stratix GX

0X001F0000

Abstract: POF Formats Altera 0x00010040 stratus EPC16 LHF16J06
Contextual Info: 12. Remote System Configuration with Stratix & Stratix GX Devices S52015-3.1 Introduction Altera Stratix® and Stratix GX devices are the first programmable logic devices PLDs featuring dedicated support for remote system configuration. Using remote system configuration, a Stratix or Stratix GX

EP20K200E

Abstract: EP20K400E
Contextual Info: 10. Transitioning APEX Designs to Stratix & Stratix GX Devices S52012-3.0 Introduction Stratix and Stratix GX devices are Altera’s next-generation, system-ona-programmable-chip SOPC solution. Stratix and Stratix GX devices simplify the block-based design methodology and bridge the gap

altera stratix II fpga

Abstract: EPCS16 EPCS64 SSTL-18 18x18-Bit
Contextual Info: White Paper Architectural Differences Between Stratix II and Stratix Devices Introduction Stratix II devices, Altera's next-generation high-density FPGAs, are based on the award-winning Stratix device architecture. Building on the innovations that made Stratix FPGAs an instant success, Stratix II devices provide new

pin configuration 1K variable resistor

Abstract: TMs 1122 pin configuration 20K variable resistor EP1S60 EPC16
Contextual Info: 11. Configuring Stratix & Stratix GX Devices S52013-3.2 Introduction You can configure Stratix and Stratix GX devices using one of several configuration schemes. All configuration schemes use either a microprocessor, configuration device, or a download cable. See

JESD8-15

Abstract: HSTL standards SSTL-18 class 8 date sheet EIA standards 15-V
Contextual Info: 10. Selectable I/O Standards in Stratix II and Stratix II GX Devices SII52004-4.6 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices, including: • ■ ■ ■ ■ Stratix II and Stratix II GX I/O

CY7C1313AV18-250BZC

Abstract: EP1S60 EP2S60F1020C5ES F1020 v32-88
Contextual Info: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices Application Note 326 May 2008, ver. 5.1 Introduction Synchronous static RAM SRAM architectures support the high throughput requirements of communications, networking, and digital

EP2S15

Abstract: EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS16 EPCS64 pull-up resistor 10K EPCS 16 soic
Contextual Info: 7. Configuring Stratix II & Stratix II GX Devices SII52007-4.4 Introduction Stratix II and Stratix II GX devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data must be downloaded to Stratix II and Stratix II GX devices each time the device

pin configuration of latch switch

Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS128 EPCS16 EPCS64
Contextual Info: 13. Configuring Stratix II & Stratix II GX Devices SII52007-4.5 Introduction Stratix II and Stratix II GX devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data must be downloaded to Stratix II and Stratix II GX devices each time the device

HSTL standards

Abstract: DDR2 sstl_18 class I 15-V SSTL-18
Contextual Info: 4. Selectable I/O Standards in Stratix II & Stratix II GX Devices SII52004-4.5 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices, including: • ■ ■ ■ ■ Stratix II & Stratix II GX I/O

HSTL standards

Abstract: class sstl SSTL-18 EIA standards 15-V SSTL18 JESD89A DDR2 sstl_18 class I
Contextual Info: 4. Selectable I/O Standards in Stratix II and Stratix II GX Devices SII52004-4.6 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices, including: • ■ ■ ■ ■ Stratix II and Stratix II GX I/O

AN454-3

Abstract: Quartus II Simulator
Contextual Info: Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices AN454-3.0 Application Note This application note describes the flow for implementing phase-locked loop PLL reconfiguration in Stratix III and Stratix IV devices. Use this application note in

EP2S15

Abstract: EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS128 EPCS16 EPCS64
Contextual Info: 7. Configuring Stratix II and Stratix II GX Devices SII52007-4.5 Introduction Stratix II and Stratix II GX devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data must be downloaded to Stratix II and Stratix II GX devices each time the device

Contextual Info: Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices AN454-3.2 Application Note This application note describes the flow for implementing phase-locked loop PLL reconfiguration in Stratix III and Stratix IV devices. Use this application note in

2f 1001

Abstract: 11010 OC-96
Contextual Info: 6. Specifications & Additional Information SIIGX52004-3.0 Transceiver Blocks Table 6–1 shows the transceiver blocks for Stratix II GX and Stratix GX devices and compares their features. Table 6–1. Stratix II GX Features Versus Stratix GX Features Part 1 of 2

2f 1001

Abstract: 1100 11010 FD-111 transistor D313 equivalent
Contextual Info: 6. Specifications & Additional Information SIIGX52004-3.1 Transceiver Blocks Table 6–1 shows the transceiver blocks for Stratix II GX and Stratix GX devices and compares their features. Table 6–1. Stratix II GX Features Versus Stratix GX Features Part 1 of 2

EP1S60

Contextual Info: 13. General-Purpose PLLs in Stratix & Stratix GX Devices S52001-3.2 Introduction Stratix and Stratix GX devices have highly versatile phase-locked loops PLLs that provide robust clock management and synthesis for on-chip clock management, external system clock management, and high-speed

S5200-1

Abstract: EP1S60 S52001-3
Contextual Info: 1. General-Purpose PLLs in Stratix & Stratix GX Devices S52001-3.2 Introduction Stratix and Stratix GX devices have highly versatile phase-locked loops PLLs that provide robust clock management and synthesis for on-chip clock management, external system clock management, and high-speed

JESD87

Abstract: CMOS applications handbook programmable peripheral Interface pentium JC42 P802 SSTL-18
Contextual Info: 4. Selectable I/O Standards in Stratix & Stratix GX Devices S52004-3.4 Introduction The proliferation of I/O standards and the need for higher I/O performance have made it critical that devices have flexible I/O capabilities. Stratix and Stratix GX programmable logic devices PLDs

EP1S60

Abstract: Shift Registers
Contextual Info: 14. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices S52003-3.3 Introduction Stratix and Stratix GX devices feature the TriMatrix memory structure, composed of three sizes of embedded RAM blocks. TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit

CY7C1313V18

Abstract: EP1S60 RLDRAM
Contextual Info: 3. External Memory Interfaces in Stratix & Stratix GX Devices S52008-3.3 Introduction Stratix and Stratix GX devices support a broad range of external memory interfaces such as double data rate DDR SDRAM, RLDRAM II, quad data rate (QDR) SRAM, QDRII SRAM, zero bus turnaround (ZBT)

embedded control handbook

Abstract: EP1S60
Contextual Info: 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices S52003-3.3 Introduction Stratix and Stratix GX devices feature the TriMatrix memory structure, composed of three sizes of embedded RAM blocks. TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit