STR W 6553 Search Results

C4094

Abstract: CD54HC4094 CD54HC4094F3A CD74HC4094 CD74HC4094E CD74HC4094M CD74HC4094M96 CD74HCT4094
Contextual Info: [ /Title CD74H C4094, CD74H CT4094 /Subject (High Speed CMOS Logic 8- CD54HC4094, CD74HC4094, CD74HCT4094 Data sheet acquired from Harris Semiconductor SCHS211C November 1997 - Revised May 2003 High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

PJ 976 lv

Abstract: DS90UH926Q
Contextual Info: J / l T exas * In stru m en ts DS90UH927Q 5M Hz - 85M Hz 24-bit C olor FPD -Link III S erializer w ith HDCP General Description Features The DS90UH927Q serializer, in conjunction with a DS90UH928Q or DS90UH926Q deserializer, provides a so­ lution for secure distribution of content-protected digital video

TLV411XA

Abstract: TLV41111
Contextual Info: TLV4110, TLV4111, TLV4112, TLV4113 FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS289 - DECEMBER 1999 • Rail-To-Rail Output • Wide Bandwidth TLV4112 D, DGN, OR P PACKAGE TOP VIEW - 1.5 V/(as Slew Rate 10U TŒ 1 IN -Œ Specified for:

Contextual Info: CD54HC4094, CD74HC4094, CD74HCT4094 Data sheet acquired from Harris Semiconductor SCHS211E November 1997 − Revised December 2010 High−Speed CMOS Logic 8−Stage Shift and Store Bus Register, Three−State Features ¥ Buffered Inputs [ /Title CD74H C4094,

Contextual Info: CD54HC4094, CD74HC4094, CD74HCT4094 Data sheet acquired from Harris Semiconductor SCHS211E November 1997 − Revised December 2010 High−Speed CMOS Logic 8−Stage Shift and Store Bus Register, Three−State Features ¥ Buffered Inputs [ /Title CD74H C4094,

6N140A

Contextual Info: TEXAS INSTR OPTO Wt fl^blTSb GD7b32G T • T i l t 3SE D p i f I 6N140A FO U R -C H A N N EL O PTO C O U PLER /O P TO IS O LATO R i l - D 3622, JA N U A R Y 1991

Contextual Info: CD54HC4094, CD74HC4094, CD74HCT4094 Data sheet acquired from Harris Semiconductor SCHS211E November 1997 − Revised December 2010 High−Speed CMOS Logic 8−Stage Shift and Store Bus Register, Three−State Features ¥ Buffered Inputs [ /Title CD74H C4094,

C4094

Abstract: CD54HC4094 CD54HC4094F3A CD74HC4094 CD74HC4094E CD74HC4094M CD74HC4094MT CD74HCT4094
Contextual Info: CD54HC4094, CD74HC4094, CD74HCT4094 Data sheet acquired from Harris Semiconductor SCHS211E November 1997 − Revised December 2010 High−Speed CMOS Logic 8−Stage Shift and Store Bus Register, Three−State Features ¥ Buffered Inputs [ /Title CD74H C4094,

HC4094M

Contextual Info: CD54HC4094, CD74HC4094, CD74HCT4094 Data sheet acquired from Harris Semiconductor SCHS211E November 1997 − Revised December 2010 High−Speed CMOS Logic 8−Stage Shift and Store Bus Register, Three−State Features ¥ Buffered Inputs [ /Title CD74H C4094,

CD74HC4094

Contextual Info: CD54HC4094, CD74HC4094, CD74HCT4094 Data sheet acquired from Harris Semiconductor SCHS211E November 1997 − Revised December 2010 High−Speed CMOS Logic 8−Stage Shift and Store Bus Register, Three−State Features ¥ Buffered Inputs [ /Title CD74H C4094,

d3905

Contextual Info: TL7759C SUPPLY VOLTAGE SUPERVISOR D3905. JANUARY 1991-REVISED SEPTEMBER 1991 D OR P PACKAGE TOP VIEW * Power-On Reset Generator * Automatic Reset Generation After Voltage Drop * Precision Threshold Voltage 4.55 V ±120 mV * Low Standby Current, . . 20 ^A

tlc5411

Contextual Info: TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A - OCTOBER 1983 - REVISED MARCH 1995 • 8-Bit Resolution A/D Converter • Microprocessor Peripheral or Stand-Alone Operation • On-Chip 12-Channel Analog Multiplexer

Contextual Info: SN74CBT3253 DUAL 4-BIT TO 1-BIT FET MULTIPLEXER/DEMULTIPLEXER I S C D S 0 1 8 - M AY 1995 D, DB, O R PW P A C K A G E TO P V IEW • Functionally Equivalent to QS3253 • 5 -Q Switch Connection Between Two Ports Ü E T I 1 U 16 1 V C C 15 ] OE2 S1 [ 2 14 ] S O

CXK77B1810AGB

Abstract: CXK77B1810AGB-5
Contextual Info: CXK77B1810AGB -5/6 High Speed Bi-CMOS Synchronous Static RAM Preliminary For the availability of this product, please contact the sales office. Description The CXK77B1810AGB-5/6 is a high speed 1M bit Bi-CMOS synchronous static RAM organized as 65536 words by 18 bits. This SRAM integrates input

2a930

Contextual Info: SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E - JULY 1996 - REVISED DECEMBER 1998 • State-of-the-Art Advanced BiCMOS Technology ABT Widebus Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation

Contextual Info: [ /Title CD74H C4094, CD74H CT4094 /Subject (High Speed CMOS Logic 8- CD54HC4094, CD74HC4094, CD74HCT4094 Data sheet acquired from Harris Semiconductor SCHS211D November 1997 - Revised October 2003 High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

D2B4

Abstract: H1B13
Contextual Info: SN54ABT32543, SN74ABT32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230B - JUNE 1992 - REVISED JULY 1994 • Members of the Texas Instruments Wldebus+ Family • State-of-the-Art EPIC-llB™ BICMOS Design Significantly Reduces Power Dissipation

transistor jcs

Contextual Info: ADE-207-007A Feb. 1988 HD81810 D igital Signal Processor D S P -W W ide-T em perature-R ange H ITA C H I The HD81810/HD81A810 is m em ber of th e DSP fam ily of single-chip general-purpose digital signal processors w hich can be u sed in th e w ide-ran ge am bient tem perature. H igh­

Contextual Info: SN54ALVTH16827, SN74ALVTH16827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES076E - JULY 1996 - REVISED DECEMBER 1998 • State-of-the-Art Advanced BiCMOS Technology ABT Widebus Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation

P34S8

Abstract: 74ACT11648
Contextual Info: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS115 - P34S8, MARCH 1990 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible DW PACKAGE TOP VIEW Independent Registers A and B Buses _ J — o — u G [ 1 28 ] C A B Multiplexed Real-Time and Stored Data

Contextual Info: SN74LVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE JANUARY 1993 D, DB, OR PW PACKAGE TOP VIEW 1A [ 1 EPIC (Enhanced-Performance Implanted CMOS) Submicron Process • Designed to Facilitate Incident Wave Switching for Line Impedances of 50 Q or Greater •

Contextual Info: SN74LVC04 HEX INVERTER JANUARY 1993 1A [ 1 EPIC Enhanced-Performance Implanted CMOS Submicron Process • Designed to Facilitate Incident Wave Switching for Line Impedances of 50 Q or Greater • Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, Ta = 25°C

Contextual Info: SN74LVC04 HEX INVERTER SCAS281 - JANUARY 1993 - REVISED MARCH 1994 • EP/C Enhanced-Performance Implanted CMOS Submicron Process D, DB, OR PW PACKAGE (TOP VIEW) • Typical Vq lp (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C | 1A [ 1Y[ 2A [

Contextual Info: SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS S C E S 138A - JULY 1998 - REVISED JANUARY 1999 • State-of-the-Art Advanced BiCMOS Technology ABT Widebus Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation