STM MARKING Search Results

D1 3009k

Abstract: 6 pin 2D 1002 ring COUNTER
Contextual Info: IBM3009K2672 IBM SONET/SDH Framer Features • Integrated clock recovery and synthesis for four OC-3c/STM-1 signals or one OC-12/OC-12c/ STM-4/STM-4c signal • OC-12/STM-4 or quad OC-3c/STM-1 framing and performance monitoring • Expansion port for OC-48/STM-16 operation

GD16591-48BA

Abstract: 10gd1 gd16591
Contextual Info: STM-4/STM-1/E4 3.3 V Multifunction Transmitter and Receiver GD16591/GD16592 Preliminary General Description Features The GD16591 and GD16592 is a frontend transmitter/receiver chip set designed for multiple line interfaces: u STM-4 / OC-12 u STM-1 / OC-3 u PDH E4

GD16592A

Abstract: GD16591A
Contextual Info: STM-4/STM-1/E4 3.3 V Multifunction Transmitter and Receiver GD16591A/GD16592A Preliminary General Description Features The GD16591A and GD16592A is a front-end transmitter/receiver chip set designed for multiple line interfaces: u STM-4 / OC-12 u STM-1 / OC-3

10gd1

Abstract: GD16592A GD16591A PFC 1.5kw GD16591A-48BA PFC 50w schematic SON-5 E4 dsel12
Contextual Info: STM-4/STM-1/E4 3.3 V Multifunction Transmitter and Receiver GD16591A/GD16592A an Intel company General Description Features The GD16591A and GD16592A is a front-end transmitter/receiver chip set designed for multiple line interfaces: u STM-4 / OC-12 u STM-1 / OC-3

GD16591A

Abstract: GD16592A GD16592A-48BA 10gd1
Contextual Info: STM-4/STM-1/E4 3.3 V Multifunction Transmitter and Receiver GD16591A/GD16592A an Intel company General Description Features The GD16591A and GD16592A is a front-end transmitter/receiver chip set designed for multiple line interfaces: u STM-4 / OC-12 u STM-1 / OC-3

GG1Q

Contextual Info: DATASHEET PM PMC-970133 ISSUE2 PRELIMINARY 1 PMC-Sierra, Inc. PMS342 spbctra -155 SONET/SDH PA YLOAD EXTRACTOR/ALIGNER FEATURES • Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-1 STM-0/AU3 , STS-3 (STM-1/AU3) or STS-3c (STM-1 /AU4) interface

AU-AIS

Abstract: Digital Alarm Clock by using ttl LXT e2 LXT6251A marking cod A2 regenerator in optical D4D12 LXT6051 LXT6051QE SSI 7200
Contextual Info: LXT6051 STM-1/0 SDH Overhead Terminator Datasheet The LXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0 51Mb/s and STM-1 (155Mb/s) multiplexers. It provides micro-controller access for performance monitoring,

Contextual Info: EtherPHAST -48 Plus Device OC-48/STM-16 SONET/SDH Ethernet Mapper TXC-06742 DATA SHEET PRODUCT PREVIEW TXC-06742-MB, Ed. 4 December 2005 FEATURES APPLICATIONS • 1x STS-48/STM-16 or 4x STS-12/STM-4 framer with TOH processing, 4x 622 LVDS line side interface

ICS894D115I-04

Abstract: led clock circuit diagram ICS894D115I-01 ICS894D115AGI-04 ICS894D115I
Contextual Info: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

Contextual Info: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

ICS894D115I-01

Abstract: tube OC3 ICS894D115BGI-01 ICS894D115I-04 ICS894D115I vsc8115 OC3 Tube
Contextual Info: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

OC3 Tube

Abstract: C813C Nippon capacitors
Contextual Info: PRELIMINARY ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

Contextual Info: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

iball

Abstract: transistor oc 76 GR-253-CORE OC48 STM16 STM-64 ZL30416 ZL30416GGG
Contextual Info: ZL30416 SONET/SDH Clock Multiplier PLL Data Sheet Features June 2004 • Low jitter clock outputs suitable for OC-192, OC48, OC-12, OC-3 and OC-1 SONET applications as defined in Telcordia GR-253-CORE • Low jitter clock outputs suitable for STM-64, STM16, STM-4 and STM-1 applications as defined in

GR-253-CORE

Abstract: OC48 STM16 STM-64 ZL30416 ZL30416GGG ZL30416GGG2
Contextual Info: ZL30416 SONET/SDH Clock Multiplier PLL Data Sheet Features • • June 2006 Low jitter clock outputs suitable for OC-192, OC48, OC-12, OC-3 and OC-1 SONET applications as defined in Telcordia GR-253-CORE Ordering Information ZL30416GGG ZL30416GGG2 Low jitter clock outputs suitable for STM-64, STM16, STM-4 and STM-1 applications as defined in

STM16

Abstract: STM-64 ZL30416 ZL30416GGG GR-253-CORE OC48
Contextual Info: ZL30416 SONET/SDH Clock Multiplier PLL Data Sheet Features November 2004 • Low jitter clock outputs suitable for OC-192, OC48, OC-12, OC-3 and OC-1 SONET applications as defined in Telcordia GR-253-CORE • Low jitter clock outputs suitable for STM-64, STM16, STM-4 and STM-1 applications as defined in

iball

Abstract: STM-64 ZL30416 ZL30416GGG ZL30416GGG2 GR-253-CORE OC48 STM16
Contextual Info: ZL30416 SONET/SDH Clock Multiplier PLL Data Sheet Features • • June 2006 Low jitter clock outputs suitable for OC-192, OC48, OC-12, OC-3 and OC-1 SONET applications as defined in Telcordia GR-253-CORE Ordering Information ZL30416GGG ZL30416GGG2 Low jitter clock outputs suitable for STM-64, STM16, STM-4 and STM-1 applications as defined in

Contextual Info: DATA SHEET PM PMC-970133 ISSUE 4 1 PMC-Sierra, Inc. PM5342 s p e c t r a -155 SONET/SDH PA YLOAD EXTRACTOR/ALIGNER FEATURES • Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-1 STM-0/AU3 , STS-3 (STM-1/AU3) or STS-3c (STM-1/AU4) interface applications, operating at serial interface speeds of up to 155.52 Mbit/s.

diode GFP AA

Abstract: KT 208 sierra The SDH interface in AXE MQE vco ss19 810 DD107* CONVERTER WD 969 TAA 611 T12 ic tb 810 datasheet hp 9720
Contextual Info: D A TA S H E E T PM PM C -970133 IS S U E 2 n /K PR ELIM INA R Y 1 PMC-Sierra, Inc. PM5342 s p e c tra -155 SO N ET/SDH PA YLO AD EXTRACTO R/ALIG NER FEATURES • Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-1 STM-0/AU3 , STS-3 (STM-1/AU3) or STS-3c (STM-1/AU4) interface

M25N-2

Abstract: V3-V24
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 Features • Dual Mode STS-48c/STM-16c to Packet/ ATM Framing Device for User Network Interface and Network Node Interface Applications • Prepared for STS-192/STM-64 Applications

Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 Features • Dual Mode STS-48c/STM-16c to Packet/ ATM Framing Device for User Network Interface and Network Node Interface Applications • Prepared for STS-192/STM-64 Applications

cell broadband

Abstract: MC68360 MC92500 MC92501 MPC860 MPC860SAR 1098M
Contextual Info: Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview MC92501 OC-3/STM-1 ATM Cell Processor ATMC Freescale Semiconductor, Inc. The OC-3/STM-1 ATMC is a highly integrated ATM layer processor that combines such functions as OAM, policing, address translation, and

D12RDB

Abstract: STS-48 VSC9112 CRC-32 GR-253-CORE STS-192
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 Features • Prepared for STS-192/STM-64 Applications • Dual Mode STS-48c/STM-16c to Packet/ ATM Framing Device for User Network Interface and Network Node Interface Applications

multiplexing e1 frame to e3 frame

Abstract: S1215P S1215 STM MARKING GR-253 TU12 32xDS1
Contextual Info: Product Brief 5 21 S1 UR AM S1215 Amur Deep channelization SONET/SDH to PDH framer and 1K Channels HDLC/ATM/GFP processor Overview SONET/SDH Line Features Tributary Features S1215 (Amur) interfaces with 155Mbps/622Mbps SONET/SDH (1xSTS-12/STM-4, 4xSTS-3/STM-1)