SSTL-15 CLASS I Search Results

LFXP2-17E-5QN208C

Abstract: lfxp2-5e-5ftn256c lfxp2-5e-5tn144c LFXP2-8E-5FTN256I 16X4 XP2-17 LFXP2-40E LFXP2-5E-6TN144C sequential gearbox LFXP2-8E-5TN144I
Contextual Info: LatticeXP2 Family Data Sheet DS1009 Version 01.7, April 2011 LatticeXP2 Family Data Sheet Introduction February 2008 Data Sheet DS1009  Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II

LFXP2-17E-5QN208C

Abstract: FTN256 lfxp2-5e LFXP2-5E-5QN208C LFXP2-8E-6FTN256C lfxp2-8E LFXP2-30E-6FTN256C XP2 LFXP2-5E-5QN208C LFXP2-30E-5FTN256I LFXP2-5E-5FTN256C
Contextual Info: LatticeXP2 Family Data Sheet DS1009 Version 01.6, August 2008 LatticeXP2 Family Data Sheet Introduction February 2008 Data Sheet DS1009 • Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II

Contextual Info: LatticeXP2 Family Data Sheet DS1009 Version 02.0, March 2014 LatticeXP2 Family Data Sheet Introduction February 2012 Data Sheet DS1009  Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II

Contextual Info: LatticeXP2 Family Data Sheet DS1009 Version 01.9, June 2013 LatticeXP2 Family Data Sheet Introduction February 2012 Data Sheet DS1009  Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II

FTN256

Abstract: LFXP2-30E-5FTN256I LFXP2-8E-6FTN256C LFXP2-17E-5FTN256I LFXP2-8E-5FTN256C FTBGA 256 LFXP2-17E-6FT256I8W LFXP2-17E-7FTN256C LFXP2-5E-6TN144C LFXP2-5E-7FTN256C
Contextual Info: LatticeXP2 Family Data Sheet DS1009 Version 01.4, April 2008 LatticeXP2 Family Data Sheet Introduction February 2008 Preliminary Data Sheet DS1009 • Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II

GTLP16612

Abstract: SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH1645 SN74GTLPH16612 SSTL-3 sstl lvttl Translator
Contextual Info: White Paper Using MAX 7000B Devices to Replace I/O Drivers Introduction The Altera® MAX® 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM memory interfaces.

vhdl code for ddr3

Abstract: point-to-point mini-lvds LVCMOS15 LVCMOS25 LVCMOS33 PCI33 mini-lvds source driver SSTL15D mini-lvds driver LVCMOS18
Contextual Info: LatticeECP3 sysIO Usage Guide June 2010 Technical Note TN1177 Introduction The LatticeECP3 sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and how to implement them using Lattice’s ispLEVER design software.

74HC230

Abstract: HC210 BGA-614 EP2S180 EP2S30 EP2S60 EP2S90 HC220 HC230 HC240
Contextual Info: 8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.4 Introduction Altera HardCopy® II devices and Stratix® II devices are both manufactured on a 1.2-V, 90-nm process technology and offer many similar features. Designers can use the Quartus® II software to migrate

EP2S90

Abstract: HC210 Stratix II EP2S60 HC220 HC230 HC240 EP2S180 EP2S30 EP2S60
Contextual Info: 8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.3 Introduction Altera HardCopy® II devices and Stratix® II devices are both manufactured on a 1.2-V, 90-nm process technology and offer many similar features. Designers can use the Quartus® II software to migrate

TLK3114SA

Contextual Info: DLKPC192S 10ĆGbps ETHERNET LAN PHYSICAL CODING SUBLAYER PCS WITH SSTL XGMII INTERFACE SLLS536 – AUGUST 2002 D 10-Gbps Ethernet LAN PCS With 64b/66b D D ENDEC 10-Gbps Media-Independent Interface (XGMII) Using 2.5-V SSTL Class 2 Technology 10-Gbps 16-Bit Interface (XSBI) Using LVDS

GTLP16612

Abstract: GTLP16T1655 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH16612
Contextual Info: Using MAX 7000B Devices to Replace I/O Drivers December 2002, ver. 1.0 Introduction Application Note 293 The Altera MAX® 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM memory interfaces.

interfacing differential logic families 1998

Abstract: 15-V SSTL-18 HSTL standards
Contextual Info: Section IV. I/O Standards This section provides information on Stratix II GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Stratix II & Stratix II GX

TLK3114SA

Contextual Info: DLKPC192S 10ĆGbps ETHERNET LAN PHYSICAL CODING SUBLAYER PCS WITH SSTL XGMII INTERFACE SLLS536 − AUGUST 2002 D 10-Gbps Ethernet LAN PCS With 64b/66b D D ENDEC 10-Gbps Media-Independent Interface (XGMII) Using 2.5-V SSTL Class 2 Technology 10-Gbps 16-Bit Interface (XSBI) Using LVDS

ttl to mini-lvds

Abstract: EP2C5 mini lvds CII51010-2 EP2C20 EP2C35 EP2C50 SSTL-18 SSTL IO pad
Contextual Info: Section IV. I/O Standards This section provides information on Cyclone II single-ended, voltage referenced, and differential I/O standards. This section includes the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Cyclone II Devices

PLL 4046 4011 4017

Abstract: phase angle controller SIII52001-1 SSTL-15 SSTL-18
Contextual Info: Stratix III Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V2-1.3 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

DDR2 sstl_18 class

Abstract: HSTL standards 15-V SSTL-18 N098
Contextual Info: Section III. I/O Standards This section provides information on Stratix II single-ended, voltagereferenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 4, Selectable I/O Standards in Stratix II and Stratix II GX

HSTL standards

Abstract: 15-V SSTL-18
Contextual Info: Section IV. I/O Standards This section provides information on Stratix II GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Stratix II and Stratix II GX

LVCMOS15

Abstract: LVCMOS25 LVCMOS33 PCI33 SSTL18II
Contextual Info: LatticeXP2 sysIO Usage Guide June 2010 Technical Note TN1136 Introduction The LatticeXP2 sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and how they can be implemented using Lattice’s ispLEVER design software.

SSTL "on-chip termination" 1998

Abstract: 15-V SSTL-18 DDR2 SDRAM sstl_18 HSTL standards
Contextual Info: Section III. I/O Standards This section provides information on Stratix II single-ended, voltagereferenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 4, Selectable I/O Standards in Stratix II & Stratix II GX

SSTL-15

Abstract: mini-lvds EIA-644 SSTL-18 EP3SL70
Contextual Info: 7. Stratix III Device I/O Features SIII51007-1.9 Stratix III I/Os are specifically designed for ease of use and rapid system integration while simultaneously providing the high bandwidth required to maximize internal logic capabilities and produce system-level performance. Independent modular I/O

PLL 4046 4011 4017

Abstract: 5252 F 1107 SSTL-15 SIII52001-1 SSTL-18 4046 PLL Designers Guide 0906NS DDR SDRAM Controller VCO 1430 2230 MHz
Contextual Info: 1. Stratix III Device Datasheet: DC and Switching Characteristics SIII52001-1.3 Electrical Characteristics Operating Conditions When Stratix III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible

LVCMOS25

Abstract: LVCMOS15 LVCMOS33 LVCMOS18 ECP2M date sheet of ninth class
Contextual Info: LatticeECP2/M sysIO Usage Guide June 2010 Technical Note TN1102 Introduction The LatticeECP2 and LatticeECP2M™ sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and

TLK3114SA

Contextual Info: DLKPC192S 10ĆGbps ETHERNET LAN PHYSICAL CODING SUBLAYER PCS WITH SSTL XGMII INTERFACE SLLS536 – AUGUST 2002 D 10-Gbps Ethernet LAN PCS With 64b/66b D D ENDEC 10-Gbps Media-Independent Interface (XGMII) Using 2.5-V SSTL Class 2 Technology 10-Gbps 16-Bit Interface (XSBI) Using LVDS

mini-lvds source driver

Abstract: ttl to mini-lvds EP2C5 HSTL standards linear handbook mini lvds national semiconductor handbook CII51010-2 EP2C20 EP2C35
Contextual Info: Section IV. I/O Standards This section provides information on Cyclone II single-ended, voltage referenced, and differential I/O standards. This section includes the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Cyclone II Devices