SSTL IO Search Results
SSTL IO Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
|---|---|---|---|---|---|
| MR8251A/B |
|
8251A - Serial I/O Controller, 2 Channel(s), HMOS, CDIP28 - Dual marked (5962-87548023A) |
|
||
| D8274 |
|
8274 - Multi-Protocol Serial Controller (MPSC) |
|
||
| LD8274 |
|
LD8274 - Multi Protocol Controller, 2 Channel(s), 0.107421875MBps, HMOS, CDIP40 |
|
||
| MD82C59A/B |
|
82C59A - Interrupt Controller, 80C86, 80C88, 80C286, 8080, 8085, 8086, 8088, 80286, NSC800 Compatible, CMOS, CDIP28 |
|
||
| IXF1002EDT-G |
|
IXF1002 - Dual Port Gigabit Ethernet Controller |
|
SSTL IO Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
G2992F1U
Abstract: circuit diagram of ddr ram G2992 2N7002 SSTL-18 v5856 jedec MS-012-AA
|
Original |
G2992 G2992 SSTL-18, 41TYP 016TYP 27TYP 05TYP G2992F1U circuit diagram of ddr ram 2N7002 SSTL-18 v5856 jedec MS-012-AA | |
|
Contextual Info: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational |
Original |
G2996 G2996 SSTL-18 | |
power filter 25v
Abstract: G2996 G2996F1UF G2996F1U G2996P1U SSTL-18
|
Original |
G2996 G2996 SSTL-18 power filter 25v G2996F1UF G2996F1U G2996P1U SSTL-18 | |
|
Contextual Info: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational |
Original |
G2996 G2996 SSTL-18 | |
|
Contextual Info: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational |
Original |
G2996 G2996 SSTL-18 | |
|
Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM. |
Original |
UR5595 UR5595 QW-R502-062 | |
LP2995M
Abstract: c151c LP2995 LP2995LQ LP2995LQX LP2995MR LP2995MRX LP2995MX M08A
|
Original |
LP2995 exte151° LLP-16 100pF LP2995 16-Lead LQA16A LP2995M c151c LP2995LQ LP2995LQX LP2995MR LP2995MRX LP2995MX M08A | |
LP2995
Abstract: LP2995LQ LP2995LQX LP2995M LP2995MR LP2995MRX LP2995MX M08A
|
Original |
LP2995 LP2995 LP2995LQ LP2995LQX LP2995M LP2995MR LP2995MRX LP2995MX M08A | |
northbridge
Abstract: LP2995 LP2995LQ LP2995LQX LP2995M LP2995MX M08A
|
Original |
LP2995 LP2995 northbridge LP2995LQ LP2995LQX LP2995M LP2995MX M08A | |
|
Contextual Info: LP2998 LP2998 DDR-I and DDR-II Termination Regulator Literature Number: SNVS521G LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of |
Original |
LP2998 LP2998 SNVS521G SSTL-18 | |
|
Contextual Info: IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O IDT74SSTVF16857 FEATURES: DESCRIPTION: • • • • • • • • The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V |
Original |
IDT74SSTVF16857 14-BIT IDT74SSTVF16857 100mA MIL-STD-883, 200pF, SSTVF16857 310mV | |
SSTV16857Contextual Info: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 PRELIMINARY 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs |
Original |
IDT74SSTV16857 14-BIT 100mA MIL-STD-883, 200pF, SSTV16857 310mV | |
LP2994
Abstract: LP2994M LP2994MX M08A
|
Original |
LP2994 LP2994 CSP-9-111S2) CSP-9-111S2. LP2994M LP2994MX M08A | |
|
Contextual Info: {¡J PERICOM PI3B3863 . 3.3V, 10-Bit, 2-Port BusSwitch with SSTL-2 Enable |
OCR Scan |
24-pin PI3B3863 10-Bit, PI3B3863 PS8167B | |
|
|
|||
|
Contextual Info: CM3202-02 DDR VDDQ and VTT Termination Voltage Regulator Product Description The CM3202−02 is a dual−output low noise linear regulator designed to meet SSTL−2 and SSTL−3 specifications for DDR−SDRAM VDDQ supply and termination voltage VTT supply. |
Original |
CM3202-02 CM3202-02/D | |
LP2995M
Abstract: LP2995MRX LP2995MX M08A LP2995 LP2995LQ LP2995LQX LP2995MR PSOP8
|
Original |
LP2995 CSP-9-111C2) CSP-9-111S2) LP2995M LP2995MRX LP2995MX M08A LP2995LQ LP2995LQX LP2995MR PSOP8 | |
LP2994
Abstract: LP2994M LP2994MX M08A
|
Original |
LP2994 LP2994 LP2994M LP2994MX M08A | |
CSPT857C
Abstract: IDT74SSTVF16857 SSTVF16857
|
Original |
IDT74SSTVF16857 14-BIT 100mA MIL-STD-883, 200pF, SSTVF16857 310mV CSPT857C IDT74SSTVF16857 | |
SSTV16857
Abstract: IDT74SSTV16857
|
Original |
IDT74SSTV16857 14-BIT 100mA MIL-STD-883, 200pF, SSTV16857 310mV IDT74SSTV16857 | |
|
Contextual Info: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 PRELIMINARY 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs |
Original |
IDT74SSTV16857 14-BIT 100mA MIL-STD-883, 200pF, SSTV16857 310mV | |
|
Contextual Info: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 PRELIMINARY 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs |
Original |
IDT74SSTV16857 14-BIT 100mA MIL-STD-883, 200pF, SSTV16857 310mV | |
LP2995MContextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. |
Original |
LP2995 LP2995M | |
LP2995M
Abstract: LP2995 LP2995LQ LP2995MR LP2995MRX LP2995MX M08A
|
Original |
LP2995 LP2995 LP2995M LP2995LQ LP2995MR LP2995MRX LP2995MX M08A | |
LP2995Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The |
Original |
LP2995 | |