SSTL IO Search Results

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.

Contextual Info: IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: IDT74SSTVF16857 DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class I style data inputs/outputs

Contextual Info: IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs

Contextual Info: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications

JESD79C

Abstract: MARKING 3D regulator MARKING 3D regulator 5V CM3205 CM3205-00TN CM3205-00TP
Contextual Info: PRELIMINARY CM3205 DDR VDDQ and Termination Voltage Regulator Features Product Description • • • • • • • • • The CM3205 is a dual-output, low noise linear regulator designed to meet SSTL-2 and SSTL-3 specifications for DDR-SDRAM VDDQ supply and termination

IDT74SSTU32864D

Contextual Info: IDT74SSTU32864D 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FEATURES: IDT74SSTU32864D DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs

SSTV16857

Contextual Info: Preliminary Revised April 2000 SSTV16857 14-Bit Register with SSTL-2 Compatible I/O and Reset Preliminary General Description Features The SSTV16857 is a 14-bit register designed for use with 184 and 232 pin DDR-I memory modules. The device has a differential input clock, SSTL-2 compatible data inputs

Q1B-Q13B

Abstract: SSTV16859
Contextual Info: Revised March 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible

SSTV16859

Contextual Info: Revised August 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible

Contextual Info: SN74SSTL16837A 20-BIT SSTL 3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS S C BS 675G - S E P TE M B E R 1996 - R EVISED S E P TE M B E R 1998 Member of the Texas Instruments Widebus Family DGG PACKAGE TOP VIEW Supports SSTL 3 Signal Inputs and

C 151 C

Abstract: LP2995M
Contextual Info: February 2002 LP2995 DDR Termination Regulator General Description Features The LP2995 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot

Contextual Info: HM5216808C Series HM5216408C Series 1,048,576-word x 8-bit x 2-bank Synchronous Dynamic RAM SSTL-3 2,097,152-word x 4-bit x 2-bank Synchronous Dynamic RAM (SSTL-3) HITACHI ADE-203-617 (Z) Preliminary Rev. 0.0 Jul. 10, 1996 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5216808C Series,

SMD 7014

Contextual Info: www.fairchildsemi.com ML6554 3A Bus Termination Regulator Features Description • Can source and sink up to 3A, no heat sink required • Integrated Power MOSFETs • Generates termination voltages for DDR SDRAM, SSTL-2 SDRAM, SGRAM, or equivalent memories

UR5596

Abstract: UR5596L-S08-R UR5596L-S08-T UR5596-S08-R UR5596-S08-T northbridge
Contextual Info: UNISONIC TECHNOLOGIES CO.,LTD UR5596 MOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can

857l

Abstract: SY55857L SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR SY58021U
Contextual Info: Micrel, Inc. SuperLite SY55857L SuperLite™ 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SY55857L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature:

Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device which provides a complete solution for DDR termination designs while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM

SR CAP

Abstract: sc2595strt SC2595 SC2595EVB ST EF 017
Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

857L

Contextual Info: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SuperLite SY55857L FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle

km416s4031ct-g

Contextual Info: Preliminary CMOS SDRAM KM416S4031C 1M x 16Bit x 4 Banks Synchronous DRAM with SSTL interface FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • SSTL_3 Class II compatible with multiplexed address • Four banks operation • MRS cycle with address key programs

20HTSSOP

Abstract: Q1/BSS138 BSS138 TPS51100 TPS51116 TPS54372 TPS54672 TPS54872 TPS54972
Contextual Info: Active Bus Termination Solutions DDR/QDR/GTL/SSTL/HSTL SLVT149A Texas Instruments offers a wide selection of Active Bus Termination solutions from LDOs and switching controllers to Plug-In Power. To aid in product selection, TI provides the solution recommendations in the tables below and offers

Contextual Info: SN74CBTLV3857 LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS S C D S 0 8 5 A -O C T O B E R 1 9 9 8 - R EVISED FEB R U AR Y 1999 • Enable Signal Is SSTL 2 Compatible • Flow-Through Architecture Optimizes PCB Layout • Designed For Use With 200 Mbit/s Double

qimonda

Abstract: PC2-4200P-444 PC2-4200P-444-12-ZZ HYS72T512341HHP PC2-3200P-333 HYS72T512341HKP
Contextual Info: December 2006 HYS72T512341HHP–[3.7/5]–B HYS72T512341HJP–[3.7/5]–B HYS72T512341HKP–[3.7/5]–B 240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RoHs Compliant Products Internet Data Sheet Rev. 1.0 Internet Data Sheet HYS72T512341H[H/J/K]P-[3.7/5]-B

Contextual Info: September 2006 HYS64D 128021 [ E/ H ] B DL – 5 – C HYS64D 128021 [ E/ H ] B DL – 6 – C 200-Pin-Small-Outline Double-Data-Rate SDRAM SO-DIMM DDR SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.11 Internet Data Sheet HYS64D128021[E/H]BDL–[5/6]–C

LGA 2011 Socket diagram

Abstract: BR17
Contextual Info: Intel Core i7 Processor Family for the LGA-2011 Socket Datasheet, Volume 1 Supporting Desktop Intel® Core™ i7-3960X and i7-3970X Extreme Edition Processor for the LGA-2011 Socket Supporting Desktop Intel® Core™ i7-39xxK and i7-38xx Processor Series