SSTL IO Search Results
SSTL IO Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| MR8251A/B |
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8251A - Serial I/O Controller, 2 Channel(s), HMOS, CDIP28 - Dual marked (5962-87548023A) |
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| D8274 |
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8274 - Multi-Protocol Serial Controller (MPSC) |
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| LD8274 |
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LD8274 - Multi Protocol Controller, 2 Channel(s), 0.107421875MBps, HMOS, CDIP40 |
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| MD82C59A/B |
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82C59A - Interrupt Controller, 80C86, 80C88, 80C286, 8080, 8085, 8086, 8088, 80286, NSC800 Compatible, CMOS, CDIP28 |
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| IXF1002EDT-G |
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IXF1002 - Dual Port Gigabit Ethernet Controller |
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SSTL IO Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM. |
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UR5595 UR5595 QW-R502-062 | |
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Contextual Info: IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: IDT74SSTVF16857 DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class I style data inputs/outputs |
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IDT74SSTVF16857 14-BIT 100mA MIL-STD-883, 200pF, SSTVF16857 310mV | |
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Contextual Info: IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs |
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IDT74SSTV16859 13-BIT 26-BIT 100mA MIL-STD-883, 200pF, SSTV16859 | |
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Contextual Info: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications |
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LP2998/LP2998-Q1 SNVS521J LP2998/LP2998-Q1 LP2998 SSTL-18 | |
JESD79C
Abstract: MARKING 3D regulator MARKING 3D regulator 5V CM3205 CM3205-00TN CM3205-00TP
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CM3205 CM3205 600-mV O252-5 JESD79C MARKING 3D regulator MARKING 3D regulator 5V CM3205-00TN CM3205-00TP | |
IDT74SSTU32864DContextual Info: IDT74SSTU32864D 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FEATURES: IDT74SSTU32864D DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs |
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IDT74SSTU32864D 100mA MIL-STD-883, 200pF, 96-pin SSTU32864D 25-bit 14-bit 10MHz, IDT74SSTU32864D | |
SSTV16857Contextual Info: Preliminary Revised April 2000 SSTV16857 14-Bit Register with SSTL-2 Compatible I/O and Reset Preliminary General Description Features The SSTV16857 is a 14-bit register designed for use with 184 and 232 pin DDR-I memory modules. The device has a differential input clock, SSTL-2 compatible data inputs |
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SSTV16857 14-Bit | |
Q1B-Q13B
Abstract: SSTV16859
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SSTV16859 13-Bit Q1B-Q13B | |
SSTV16859Contextual Info: Revised August 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible |
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SSTV16859 13-Bit | |
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Contextual Info: SN74SSTL16837A 20-BIT SSTL 3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS S C BS 675G - S E P TE M B E R 1996 - R EVISED S E P TE M B E R 1998 Member of the Texas Instruments Widebus Family DGG PACKAGE TOP VIEW Supports SSTL 3 Signal Inputs and |
OCR Scan |
SN74SSTL16837A 20-BIT | |
C 151 C
Abstract: LP2995M
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LP2995 C 151 C LP2995M | |
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Contextual Info: HM5216808C Series HM5216408C Series 1,048,576-word x 8-bit x 2-bank Synchronous Dynamic RAM SSTL-3 2,097,152-word x 4-bit x 2-bank Synchronous Dynamic RAM (SSTL-3) HITACHI ADE-203-617 (Z) Preliminary Rev. 0.0 Jul. 10, 1996 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5216808C Series, |
OCR Scan |
HM5216808C HM5216408C 576-word 152-word ADE-203-617 Hz/100 Hz/83 7777K\ | |
SMD 7014Contextual Info: www.fairchildsemi.com ML6554 3A Bus Termination Regulator Features Description • Can source and sink up to 3A, no heat sink required • Integrated Power MOSFETs • Generates termination voltages for DDR SDRAM, SSTL-2 SDRAM, SGRAM, or equivalent memories |
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ML6554 ML6554 DS30006554 SMD 7014 | |
UR5596
Abstract: UR5596L-S08-R UR5596L-S08-T UR5596-S08-R UR5596-S08-T northbridge
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UR5596 UR5596 QW-R502-045 UR5596L-S08-R UR5596L-S08-T UR5596-S08-R UR5596-S08-T northbridge | |
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857l
Abstract: SY55857L SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR SY58021U
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SY55857L 200ps 400ps 46mW/channel 10-pin SY55857L M9999-082306 857l SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR SY58021U | |
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Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device which provides a complete solution for DDR termination designs while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM |
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SC2595 | |
SR CAP
Abstract: sc2595strt SC2595 SC2595EVB ST EF 017
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SC2595 SC2595 IPC-SM-782A, SR CAP sc2595strt SC2595EVB ST EF 017 | |
857LContextual Info: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SuperLite SY55857L FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle |
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SY55857L 200ps 400ps 46mW/channel 10-pin SY55857L 857L | |
km416s4031ct-gContextual Info: Preliminary CMOS SDRAM KM416S4031C 1M x 16Bit x 4 Banks Synchronous DRAM with SSTL interface FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • SSTL_3 Class II compatible with multiplexed address • Four banks operation • MRS cycle with address key programs |
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KM416S4031C 16Bit KM416S4031C A10/AP km416s4031ct-g | |
20HTSSOP
Abstract: Q1/BSS138 BSS138 TPS51100 TPS51116 TPS54372 TPS54672 TPS54872 TPS54972
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SLVT149A TPS51116: TPS51100: PTHxx060Y TPS54372: BSS138 20HTSSOP Q1/BSS138 BSS138 TPS51100 TPS51116 TPS54372 TPS54672 TPS54872 TPS54972 | |
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Contextual Info: SN74CBTLV3857 LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS S C D S 0 8 5 A -O C T O B E R 1 9 9 8 - R EVISED FEB R U AR Y 1999 • Enable Signal Is SSTL 2 Compatible • Flow-Through Architecture Optimizes PCB Layout • Designed For Use With 200 Mbit/s Double |
OCR Scan |
SN74CBTLV3857 10-BIT | |
qimonda
Abstract: PC2-4200P-444 PC2-4200P-444-12-ZZ HYS72T512341HHP PC2-3200P-333 HYS72T512341HKP
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HYS72T512341HHP HYS72T512341HJP HYS72T512341HKP 240-Pin HYS72T512341H HYS672T512341HJP- HYS72T512341HKP- qimonda PC2-4200P-444 PC2-4200P-444-12-ZZ HYS72T512341HHP PC2-3200P-333 HYS72T512341HKP | |
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Contextual Info: September 2006 HYS64D 128021 [ E/ H ] B DL – 5 – C HYS64D 128021 [ E/ H ] B DL – 6 – C 200-Pin-Small-Outline Double-Data-Rate SDRAM SO-DIMM DDR SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.11 Internet Data Sheet HYS64D128021[E/H]BDL–[5/6]–C |
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HYS64D 200-Pin-Small-Outline HYS64D128021 DDR400 | |
LGA 2011 Socket diagram
Abstract: BR17
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LGA-2011 i7-3960X i7-3970X i7-39xxK i7-38xx LGA 2011 Socket diagram BR17 | |