SSTL IO Search Results

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.

LP2995

Abstract: LP2995LQ LP2995LQX LP2995M LP2995MR LP2995MRX LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

northbridge

Abstract: LP2995 LP2995LQ LP2995LQX LP2995M LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients.

Contextual Info: LP2998 LP2998 DDR-I and DDR-II Termination Regulator Literature Number: SNVS521G LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of

Contextual Info: {¡J PERICOM PI3B3863 . 3.3V, 10-Bit, 2-Port BusSwitch with SSTL-2 Enable

UR5595L

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.

Contextual Info: CM3202-02 DDR VDDQ and VTT Termination Voltage Regulator Product Description The CM3202−02 is a dual−output low noise linear regulator designed to meet SSTL−2 and SSTL−3 specifications for DDR−SDRAM VDDQ supply and termination voltage VTT supply.

LP2995M

Abstract: LP2995MRX LP2995MX M08A LP2995 LP2995LQ LP2995LQX LP2995MR PSOP8
Contextual Info: General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

LP2994

Abstract: LP2994M LP2994MX M08A
Contextual Info: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

LP2995M

Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients.

LP2995M

Abstract: LP2995 LP2995LQ LP2995MR LP2995MRX LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

LP2995

Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

LP2995

Abstract: LP2995LQ LP2995LQX LP2995M LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients.

Contextual Info: IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: IDT74SSTVF16857 DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class I style data inputs/outputs

Contextual Info: IDT74SSTVM16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 13-BIT TO 26-BIT REGISTERED IDT74SSTVM16859 BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 1:2 register buffer Meets or exceeds JEDEC standard SSTVM16859

IDT74SSTV16859

Abstract: Q11A Q13A SSTV16859
Contextual Info: IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: IDT74SSTV16859 DESCRIPTION: • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs

Contextual Info: OBSOLETE LP2994 www.ti.com SNVS202C – MAY 2002 – REVISED APRIL 2013 DDR Termination Regulator Check for Samples: LP2994 FEATURES DESCRIPTION • • • • • • • The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3

CM3212

Abstract: CM321 02SM2 CM3212-02DE
Contextual Info: PRELIMINARY CM3212 DDR VDDQ and VTT Termination Voltage Regulator Features Product Description • The CM3212 is a dual-output low noise linear regulator designed to meet SSTL-2 and SSTL-3 specifications for DDR-SDRAM VDDQ supply and termination voltage VTT supply. With integrated power MOSFETs the

Contextual Info: IDT74SSTU32864C 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FEATURES: IDT74SSTU32864C DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs

SSTV16857

Abstract: IDT74SSTV16857 SO48-2
Contextual Info: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 ADVANCE INFORMATION 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • The SSTV16857 is a 14-bit registered buffer designed for 2.3V-2.7V

Contextual Info: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications

CM3212-02DE

Contextual Info: PRELIMINARY CM3212 DDR VDDQ and VTT Termination Voltage Regulator Features Product Description • The CM3212 is a dual-output low noise linear regulator designed to meet SSTL-2 and SSTL-3 specifications for DDR-SDRAM VDDQ supply and termination voltage VTT supply. With integrated power MOSFETs the

CM3202-02

Abstract: CM3202-02SM CM320 CM3202
Contextual Info: PRELIMINARY CM3202-02 DDR VDDQ and VTT Termination Voltage Regulator Features Product Description • The CM3202-02 is a dual-output low noise linear regulator designed to meet SSTL-2 and SSTL-3 specifications for DDR-SDRAM VDDQ supply and termination voltage VTT supply. With integrated power

Contextual Info: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications