SRIA 0 Search Results

MAX514ACWI

Abstract: MAX514BCNG MAX514 MAX514ACNG MAX514AENG MAX514AEWI MAX514BCWI MAX514BENG MAX514BEWI 0s851
Contextual Info: w iy jx iy n í 9-45 76. Rev 0: 12/91 C M O S Q uad, 12-B it, S e ria l-In p u t M u ltip ly in g DAC _ A p p lic a tio n s Digital Offset/Gam Adjustm ent Arbitrary W aveform Generators Industrial Process Controls Autom atic Test Equipm ent

MAX514ACWI

Abstract: MAX400 MAX514 MAX514ACNG MAX514AENG MAX514AEWI MAX514BCNG MAX514BCWI MAX514BENG
Contextual Info: yi/i/jxi/i/i 19-4516; Rev 1; 2/97 CMOS Quad, 12-Bit, Serial-Input Multiplying DAC The M AX514 contains four 12-bit R-2R m ultiplying d ig ital-to-analog converters D ACs , each with a serial-in parallel-out shift register, a DAC register, and control logic. The M AX514’s 3-wire serial interface design mini­

MAX514ACWI

Contextual Info: >i/i>jxiyi/i 19-4516; Rev. O; 12/91 CMOS Quad, 12-Bit, S erial-Input M ultiplying DAC _ G eneral D escription The MAX514 contains four 12-bit R-2R m ultiplying digital-to-analog converters DACs , each with a serial-in parallel-out shift register, a DAC register, and control

Contextual Info: LA-LatticeECP3 Automotive Family Data Sheet Advance DS1041 Version 01.1, April 2014 LA-LatticeECP3 Automotive Family Data Sheet Introduction April 2014 Advance Data Sheet DS1041 Features  AEC-Q100 Tested and Qualified  Higher Logic Density for Increased System

Contextual Info: LA-LatticeECP3 Automotive Family Data Sheet Advance DS1041 Version 01.0, June 2013 LA-LatticeECP3 Automotive Family Data Sheet Introduction June 2013 Features Advance Data Sheet DS1041  Pre-Engineered Source Synchronous I/O • • • • DDR registers in I/O cells

LFE3-17EA

Abstract: DS1021 ECP3-35 ECP3-95 LFE3-17EA-7FN484C lfe370e6fn672i LFE3-70EA8FN672 lfe3-70e 4420 ba LFE3-70EA-7FN484C
Contextual Info: LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010 LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

fr 3709 z

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.3EA, June 2013 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.4EA, September 2013 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.6EA, March 2014 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

data sheet of IC 9290

Abstract: marking Y24 field memory
Contextual Info: S em iconductor Group Siem ens AG » MOS Consum er Electronics Preliminary 01.95 Edition Data Sheet SDA 9270 - * Field Mixer Document number V66100-M 570-X-1-7659 : • fl235b05 Date: □ D 7 ci t i 4 ö This Material Copyrighted By Its Respective Manufacturer

LD33

Abstract: multiplier accumulator MAC code VHDL a016 b24 b03 MULT18X18 SRIB16
Contextual Info: LatticeECP2/M sysDSP Usage Guide June 2010 Technical Note TN1107 Introduction This technical note discusses how to access the features of the LatticeECP2 and LatticeECP2M™ sysDSP™ Digital Signal Processing Block described in the LatticeECP2/M Family Data Sheet. Designs targeting the sysDSP Block can offer significant improvement over traditional LUT-based implementations. Table 14-1 provides an

Contextual Info: LatticeECP3 Family Handbook HB1009 Version 04.2, February 2012 LatticeECP3 Family Handbook Table of Contents February 2012 Section I. LatticeECP3 Family Data Sheet Introduction Features . 1-1

Contextual Info: LatticeECP3 Family Handbook HB1009 Version 05.0, November 2012 LatticeECP3 Family Handbook Table of Contents November 2012 Section I. LatticeECP3 Family Data Sheet Introduction Features . 1-1

Contextual Info: LatticeECP3 Family Handbook HB1009 Version 04.9, August 2012 LatticeECP3 Family Handbook Table of Contents August 2012 Section I. LatticeECP3 Family Data Sheet Introduction Features . 1-1

Contextual Info: LatticeECP3 Family Handbook HB1009 Version 05.2, May 2013 LatticeECP3 Family Handbook Table of Contents May 2013 Section I. LatticeECP3 Family Data Sheet Introduction Features . 1-1

PD78C14

Abstract: R2M 45 87AD PD78C14G 4S14S d78c14
Contextual Info: — S • 5 / — h NEC w m s s M O S Integrated Circuit m = ï T / x T x ^ ^ P D 7 8 C 1 4 A ! i l 6 t ' v F ALU, i) T ) V • yf D ROM, RAM, A / D 3 > ^ - ^ , 1 ? b t é h CM OS 8 b y h ■ v ^ D 3 > l ; , a - ; T t , t i c J: t), miy.'mmwtwütit'Xayi.—v - j :

LFXP2_8E_5FT256C

Abstract: ld33 LD33 V LD33 e LD41 lfxp2-8E LFXP2-8E-6FT256C verilog code for correlator LVCMOS25 3 tap fir filter based on mac vhdl code
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.5, February 2010 LatticeXP2 Family Handbook Table of Contents February 2010 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

Contextual Info: LatticeXP2 Family Handbook HB1004 Version 01.7, April 2008 LatticeXP2 Family Handbook Table of Contents April 2008 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

Contextual Info: LatticeECP/EC Family Handbook HB1000 Version 03.8, November 2012 LatticeECP/EC Family Handbook Table of Contents November 2012 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1