SRAM 128 X 8 Search Results

M68Z128

Abstract: M68Z128W TSOP32 3VE1
Contextual Info: M68Z128W 3V, 1 Mbit 128 Kbit x 8 Low Power SRAM with Output Enable FEATURES SUMMARY • ULTRA LOW DATA RETENTION CURRENT Figure 1. Package – 10nA (typical) – 2.0µA (max) ■ OPERATION VOLTAGE: 3.0V (+0.6 / –0.3V) ■ 128 Kbit x 8 SRAM WITH OUTPUT ENABLE

M68Z128

Abstract: TSOP32
Contextual Info: M68Z128 5V, 1 Mbit 128 Kbit x 8 Low Power SRAM with Output Enable FEATURES SUMMARY • ULTRA LOW DATA RETENTION CURRENT Figure 1. Package – 10nA (typical) – 2.0µA (max) ■ OPERATION VOLTAGE: 5.0V ± 10% ■ 128 Kbit x 8 VERY FAST SRAM WITH OUTPUT ENABLE

A6W 4d

Abstract: SRAM 6T MT58LC256K18G1 mt 1898 le
Contextual Info: ADVANCE 256K x 18. 128K x 32/36 2.5V I/O, PIPELINED. SCD SYNCBURST SRAM I^ IIC R a N MT 58 LC 256 K 18 G 1 , M T 58 LC 128 K32 G 1, MT 58 LC 128 K36 G 1 SYNCBURST SRAM 3.3V Supply, +2.5V I/O, Pipelined, Burst Counter and Single-Cycle Deselect SYNCBURST SRAM

M48Z129V

Abstract: M48Z129Y
Contextual Info: M48Z129Y* M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE

Contextual Info: POSTACI 5 • 'T :¿tL-Z3>rlLf MK48127/128 N,X -55/70/85 SCS-THOMSON •[L tM M tsM O S S G S-TH O M SO N 3QE d 1 MEG ( 1-,048,576-BIT) 128 K X 8 CMOS SRAM ADVANCE DATA ■ BYTEWYDE 128K X 8 CM O S SRAM ■ EQUAL CYCLE/ACCESS TIMES, 55,70,85NS MAX. ■ LOW V cc DATA RETENTION 2 VOLTS

M48Z129V

Abstract: M48Z129Y
Contextual Info: M48Z129Y M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE

M48Z128

Abstract: M48Z128V M48Z128Y SOH28 TSOP32
Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE

SOH28

Abstract: TSOP32 M48Z128 M48Z128V M48Z128Y
Contextual Info: M48Z128 M48Z128Y, M48Z128V 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE

Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE

M40Z300

Abstract: M48Z128 M48Z128V M48Z128Y SOH28
Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES

Contextual Info: M48Z129V 3.3 V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of

M48Z129V

Abstract: M48Z129Y
Contextual Info: M48Z129Y M48Z129V 5.0 V or 3.3 V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of

Contextual Info: 5EP -? intol ¡FX780 10 ns FLEXIogic FPGA FAMILY WITH SRAM OPTION Any CFB can be either 24V10 Logic or SRAM Block — Up to 80 Complex Macrocells — 128 x 10 SRAM Configuration — CFB Selectable 3.3V or 5V Outputs — Open-Drain Output Option High Performance FPGA Field

Contextual Info: M48Z128 M48Z128Y 5.0 V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of

M48Z129V

Abstract: M48Z129Y
Contextual Info: M48Z129Y* M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE

Contextual Info: MEMORY LOW POWER SRAM CARD PCMCIA Rei. MB98A9061 DA Ver. 4 conformable X -2Q LOW POWER STATIC RANDOM ACCESS MEMORYCARD 64 K/128 K-BYTE • DESCRIPTION The Fujitsu MB98A9061 x and MB98A9071 x are Static Random A c e i^ Memory SRAM cards capable of storing

Contextual Info: 1 2 1993 intpl ÌFX780 10 ns FLEXIogic FPGA FAMILY WITH SRAM OPTION Any CFB can be either 24V10 Logic or SRAM Block — Up to 80 Complex Macrocells — 128 x 10 SRAM Configuration — CFB Selectable 3.3V or 5V Outputs — Open-Drain Output Option 24V10 Macrocell Features

M48T128V

Abstract: M48T128Y
Contextual Info: M48T128Y M48T128V 5.0 or 3.3V, 1 Mbit 128 Kb x 8 TIMEKEEPER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY, and CRYSTAL ■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS

M48T128V

Abstract: M48T128Y circuit diagram of o rtc split ac
Contextual Info: M48T128Y M48T128V 5.0 OR 3.3V, 1 Mbit 128 Kb x 8 TIMEKEEPER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY, and CRYSTAL ■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS

M48T128V

Abstract: M48T128Y
Contextual Info: M48T128Y M48T128V* 5.0 or 3.3V, 1 Mbit 128 Kb x 8 TIMEKEEPER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY, and CRYSTAL ■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS

mcp555

Abstract: M616Z08 mcp55
Contextual Info: M616Z08 128 Kbit 8 Kbit x 16 SRAM WITH OUTPUT ENABLE FEATURES SUMMARY • OPERATION VOLTAGE: 2.34V to 3.6V ■ 8 Kbit x 16 SRAM ■ EQUAL CYCLE and ACCESS TIMES: AS FAST AS 20ns ■ TRI-STATE COMMON I/O ■ TWO WRITE ENABLE PINS ALLOW WRITING TO UPPER AND LOWER BYTES

Contextual Info: MEMORY LOW POWER SRAM CARD PCMCIA Rel.2/JEIDA Ver.4 conformable MB98A9061 x/9071 x-20 LOW POWER STATIC RANDOM ACCESS MEMORY CARD 64 K/128 K-BYTE • DESCRIPTION The Fujitsu MB98A9061x and MB98A9071x are Static Random Access Memory SRAM cards capable of storing

mcp555

Abstract: mcp55 M616Z08
Contextual Info: M616Z08 128 Kbit 8 Kbit x 16 SRAM WITH OUTPUT ENABLE FEATURES SUMMARY • OPERATION VOLTAGE: 2.34V to 3.6V ■ 8 Kbit x 16 SRAM ■ EQUAL CYCLE and ACCESS TIMES: AS FAST AS 20ns ■ TRI-STATE COMMON I/O ■ TWO WRITE ENABLE PINS ALLOW WRITING TO UPPER AND LOWER BYTES

Contextual Info: M48T129Y M48T129V 5.0 or 3.3 V, 1 Mbit 128 Kbit x 8 TIMEKEEPER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal ■ BCD coded century, year, month, day, date,