SR FLIPFLOP Search Results

verilog code for DFT

Abstract: toshiba ASIC analog to digital converter verilog code target FPGA
Contextual Info: Potential FPGA-to-Toshiba-ASIC Migration Design Guide System Solutions from Toshiba America Electronic Components, Inc. Systems Application Engineering SAE Jean Chao, Sr. MTS John Ahn, Sr. MTS Behzad Sanii, MTS Director June 2001 Revision 1 Page 1 Prepared by Systems Application Engineering Team

CDP1852

Abstract: 307SD
Contextual Info: G E SO L I D ST AT E 17E D • 3Ô7S0Ô1 002S117 T ■ High-Reliabillly CMOS LSI CDP1852/3, CDP1852C/3 "T 5Z^3'53> . c s i/ G I — ^ 24 — v D0 MODE — 2 23 - SR/SR 2 2 — D I7 010 — 3

Contextual Info: CY54FCT163T, CY74FCT163T 4-BIT BINARY COUNTERS SCCS015A – MAY 1994 – REVISED OCTOBER 2001 D D D D D D 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC TC Q0 Q1 Q2 Q3 CET PE CY54FCT163T . . . L PACKAGE TOP VIEW P0 P1 NC P2 P3 SR NC VCC TC D SR CP P0 P1 P2 P3

Contextual Info: CY54FCT163T, CY74FCT163T 4-BIT BINARY COUNTERS SCCS015A – MAY 1994 – REVISED OCTOBER 2001 D D D D D D 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC TC Q0 Q1 Q2 Q3 CET PE CY54FCT163T . . . L PACKAGE TOP VIEW P0 P1 NC P2 P3 SR NC VCC TC D SR CP P0 P1 P2 P3

A115-A

Abstract: C101 CY54FCT163T CY74FCT163CT CY74FCT163T
Contextual Info: CY54FCT163T, CY74FCT163T 4-BIT BINARY COUNTERS SCCS015A – MAY 1994 – REVISED OCTOBER 2001 D D D D D D 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC TC Q0 Q1 Q2 Q3 CET PE CY54FCT163T . . . L PACKAGE TOP VIEW P0 P1 NC P2 P3 SR NC VCC TC D SR CP P0 P1 P2 P3

Contextual Info: CY54FCT163T, CY74FCT163T 4-BIT BINARY COUNTERS SCCS015A – MAY 1994 – REVISED OCTOBER 2001 D D D D D D 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC TC Q0 Q1 Q2 Q3 CET PE CY54FCT163T . . . L PACKAGE TOP VIEW P0 P1 NC P2 P3 SR NC VCC TC D SR CP P0 P1 P2 P3

A115-A

Abstract: C101 CY54FCT163T CY74FCT163CT CY74FCT163T
Contextual Info: CY54FCT163T, CY74FCT163T 4-BIT BINARY COUNTERS SCCS015A – MAY 1994 – REVISED OCTOBER 2001 D D D D D D 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC TC Q0 Q1 Q2 Q3 CET PE CY54FCT163T . . . L PACKAGE TOP VIEW P0 P1 NC P2 P3 SR NC VCC TC D SR CP P0 P1 P2 P3

Contextual Info: CY54FCT163T, CY74FCT163T 4-BIT BINARY COUNTERS SCCS015A – MAY 1994 – REVISED OCTOBER 2001 D D D D D D 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC TC Q0 Q1 Q2 Q3 CET PE CY54FCT163T . . . L PACKAGE TOP VIEW P0 P1 NC P2 P3 SR NC VCC TC D SR CP P0 P1 P2 P3

Contextual Info: CY54FCT163T, CY74FCT163T 4-BIT BINARY COUNTERS SCCS015A – MAY 1994 – REVISED OCTOBER 2001 D D D D D D 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC TC Q0 Q1 Q2 Q3 CET PE CY54FCT163T . . . L PACKAGE TOP VIEW P0 P1 NC P2 P3 SR NC VCC TC D SR CP P0 P1 P2 P3

A115-A

Abstract: C101 CY54FCT163T CY74FCT163CT CY74FCT163T
Contextual Info: CY54FCT163T, CY74FCT163T 4-BIT BINARY COUNTERS SCCS015A – MAY 1994 – REVISED OCTOBER 2001 D D D D D D 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC TC Q0 Q1 Q2 Q3 CET PE CY54FCT163T . . . L PACKAGE TOP VIEW P0 P1 NC P2 P3 SR NC VCC TC D SR CP P0 P1 P2 P3

OD-S524-FCFPC-SM

Abstract: OD-S524-SCFPC-SM STM-16 InGaAs Photodiode 1550nm pin Photodiode preamp IC353
Contextual Info: OE HYBRID 2.48832 Gbps Receiver OD-J6888-HA01 OC-48 SR/STM-16 I-16 -1- 21st March 2001 Preliminary - Contents - 1. Product

Data Vision P135

Abstract: P104t ZP033 stk 014 transistor 4287 AB p083r DATA VISION P123 I-CUBE P2-16C P000-P007
Contextual Info: * » S B I-Cube IQX Family Data Sheet Features Description • SR A M -b a sed , in-system pro gram m ab le • S w itc h M atrix - • The IQ X fa m ily of SR A M - b a sed bit-oriented sw itch in g devices is m an u factu red u sing a 0.6ym C M O S process. These d evices offer clock speed of

OD-S524-SC-SM

Abstract: STM-16 OD-J8660-0A01 OD-J8660-HA01 OD-S524-FCPC-SM OD-S524-MUJ-SM
Contextual Info: OE HYBRID 2.48832Gbps Transmitter OD-J8660-0A01/HA01 OC-48: SR STM-16: I-16 1 Copyright C 1994-2001 NEC Corporation 11th September 2001 Rev. 0.2, Preliminary - Contents 1. PRODUCT

Digital Displays

Abstract: circuit on how to make a simple projector plasma displays Display theory 802.11 USB FPGA-based LCD driver circuit
Contextual Info: Perspective Digital Displays Programmable Logic Enables Digital Displays by Mike Nelson An overview of an important emerging market. Sr. Manager, Strategic Solutions Xilinx, Inc. mike.nelson@xilinx.com DisplaySearch Inc. forecasts that by 2005, digital displays will eclipse conventional

Truth Table 74194

Abstract: IC 74194 pin diagram 74194 ic pin diagram
Contextual Info: -File Number 1668 TechnicalData CD54/74HC194 CD54/74HCT194 High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register 00 01 D O O I— 02 — 02 03 — •03 T yp e Features: D 8L D SR-

HA01

Abstract: OD-J6860-0A01 OD-J6860-HA01 OD-S524-FCPC-SM OD-S524-MUJ-SM OD-S524-SC-SM OD-S524-MU-SM
Contextual Info: OE HYBRID 622.08Mbps Transmitter OD-J6860-0A01/ HA01 OC-12: SR and IR-1 STM-4: I-4 and S-4.1 1 Copyright C 1994-2001 NEC Corporation 11 t h September, 2001 Rev.6 - Contents 1. PRODUCT

Ic 9148

Abstract: le 9148 38-00338-A vim 838 FCT2373T FCT573T
Contextual Info: CY54/74FCT2373T CY54/74FCT2573T sr CYPRESS 8-Bit Latches • Fully compatible with TTL input and output logic levels • Sink current 12 mA Com’l , 12 mA (Mil) Source current 15 mA (Com’l), 12 mA (Mil) Features • Function and pinout compatible with

Contextual Info: B U R R -BR O W N VSP2101 sr CCD SIGNAL PROCESSOR For Digital Cameras FEATURES DESCRIPTION • CCD SIGNAL PROCESSING: Correlated Double Sampling Black Level Clamping 0 to +34dB Gain Ranging High SNR: 53dB The VSP2101Y is a complete digital camera IC, pro­

EP1800

Abstract: N5C180-90 48-MACROCELL 5C180 74HC N5C180 N5C180-70 N5C180-75 TN5C180-75 DL056
Contextual Info: in t e i 5C180 48-MACROCELL CMOS PLD High-Performance LSI Semicustom Logic Alternative for TTL and 74HC SSI and MSI Logic Programmable Registers. Can Be Configured as D, T, SR or JK Types with Individual Reset Controls Low Power; 100 ju,W Typical Standby Dissipation

EP1800

Abstract: N5C180-75 N5C180-70 N5C180-90 48-MACROCELL 5C180 74HC N5C180 TN5C180-75 Tic 4148
Contextual Info: in t e i 5C180 48-MACROCELL CMOS PLD High-Performance LSI Semicustom Logic Alternative for TTL and 74HC SSI and MSI Logic Programmable Registers. Can Be Configured as D, T, SR or JK Types with Individual Reset Controls Low Power; 100 ju,W Typical Standby Dissipation

Tektronix 2712

Abstract: 0805C104KAT2A
Contextual Info: Application Note 1817 November 2012 13.56 MHz, Class-D Half Bridge, RF Generator with DRF1400 Gui Choi Sr. Application Engineer Phone: 541-382-8028, ext. 1205 gchoi@microsemi.com INTRODUCTION The DRF1400 is a MOSFET Half Bridge HB Hybrid Device which has been optimized for efficiency and reduced

OD-J6500-0B01

Abstract: OD-J6500-HB01 OD-J6502-0B01 OD-J6502-HB01 OD-S524-FCPC-SM OD-S524-MUJ-SM OD-S524-SC-SM j6500 HB01 resistor
Contextual Info: OE HYBRID 155.52Mbps Transmitter OD-J6500-0B01/HB01 OD-J6502-0B01/HB01 OC-3: SR, IR-1 and LR-1 STM-1: I-1, S-1.1 and L-1.1 1 Copyright C 1994-2001 NEC Corporation 11 t h September, 2001 Rev.8 - Contents 1. PRODUCT NUMBER . 3

fp6102

Abstract: FP6101 EP610-30 equivalent EP610-30 FP610 EP610 TI EP610 SSI IC adder L-72 EP610-35
Contextual Info: EP610 EPLD J Features J J J J J General Description Programm able clock option for independent clocking of all registers Macrocells in d ivid u ally programmable as D, T, JK , or SR flip-flops, or for combinatorial operation Extensive third-party software and programm ing support

EP1800 LOGIC DIAGRAM

Abstract: N5C180-90
Contextual Info: in tg l 5C180 48-MACROCELL CMOS PLD • High-Performance LSI Semicustom Logic Alternative for TTL and 74HC SSI and MSI Logic ■ Programmable Registers. Can Be Configured as D, T, SR or JK Types with Individual Reset Controls ■ 48 Macrocells with Programmable I/O