SPI LVDS Search Results

spi FIFO

Abstract: IDT88P8344 DSC-6370
Contextual Info: PRODUCT BRIEF IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4 - Number of errors - Number of bytes FEATURES • • • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation

spi on parallel port

Abstract: IDT88P8342
Contextual Info: PRODUCT BRIEF IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 - Number of errors - Number of bytes FEATURES • • • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation

National smd sop 4 pin

Abstract: SPI MICROWIRE communication controller spi lm74 How to read marking code of smd IC
Contextual Info: LM74 LM74 SPI/ MICROWIRE 12-Bit Plus Sign Temperature Sensor Literature Number: SNIS107J LM74 SPI/MICROWIRE 12-Bit Plus Sign Temperature Sensor General Description Features The LM74 is a temperature sensor, Delta-Sigma analog-todigital converter with an SPI and MICROWIRE compatible

LM71 interface

Abstract: marking t16c
Contextual Info: LM71 LM71/LM71Q SPI/MICROWIRE 13-Bit Plus Sign Temperature Sensor Literature Number: SNIS125C LM71/LM71Q SPI/MICROWIRE 13-Bit Plus Sign Temperature Sensor General Description The LM71 is a low-power, high-resolution digital temperature sensor with an SPI and MICROWIRE compatible interface,

LM703

Abstract: lm70-5 lm705 T03C LM70-3
Contextual Info: LM70 LM70 SPI/MICROWIRE 10-Bit plus Sign Digital Temperature Sensor Literature Number: SNIS112F LM70 SPI/MICROWIRE 10-Bit plus Sign Digital Temperature Sensor General Description Features The LM70 is a temperature sensor, Delta-Sigma analog-todigital converter with an SPI and MICROWIRE compatible

IXP2800

Abstract: IXF1110 Gigabit Logic IXD1110 IXF1010 Gigabit Ethernet MAC SPI AN227 altera board
Contextual Info: SPI-4.2 Interoperability with the Intel IXF1110 in Stratix GX Devices May 2003, ver. 1.0 Introduction Application Note 227 The system packet interface level 4–phase 2 SPI-4.2 specification, defined by the Optical Internetworking Forum (OIF), is fast becoming the most

Xenon 175

Abstract: SFP LVDS altera PC680 PM5392 STM-64 SFP PM3388 PM3392 PM5390 hmzd connector SFP altera
Contextual Info: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices May 2003, ver. 1.0 Introduction Application Note 228 The system packet interface level 4–phase 2 SPI-4.2 specification, defined by the Optical Internetworking Forum (OIF), is fast becoming the most

D10 SMD CODE MARKING

Abstract: LM74 LM74CIM-3 LM74CIM-5 LM74CIMX-3 LM74CIMX-5 LM74CITP-3 M08A MO-211 LM74-5
Contextual Info: LM74 SPI/MICROWIRE 12-Bit Plus Sign Temperature Sensor General Description Features The LM74 is a temperature sensor, Delta-Sigma analog-todigital converter with an SPI and MICROWIRE compatible interface. The host can query the LM74 at any time to read

LM71CIMFX

Abstract: AEC-Q100 LM71 LM71CIMF MF05A SDE06A marking d10 SOT23-5
Contextual Info: LM71/LM71Q SPI/MICROWIRE 13-Bit Plus Sign Temperature Sensor General Description The LM71 is a low-power, high-resolution digital temperature sensor with an SPI and MICROWIRE compatible interface, available in the 5-pin SOT23 or the 6-pin LLP no pull back

circuit diagram 4-20ma RECEIVER

Abstract: 4-20mA to SPI Converter ADC1x1S626 4-20ma spi
Contextual Info: LMP7312 LMP7312 Precision SPI-Programmable AFE with Differential/Single-Ended Input/Output Literature Number: SNOSB32A LMP7312 Precision SPI-Programmable AFE with Differential/SingleEnded Input/Output General Description Features The LMP7312 is a digitally programmable variable gain amplifier/attenuator. Its wide input voltage range and superior

T16Q

Abstract: LM71 AEC-Q100 LM71CIMF LM71CIMFX MF05A SDE06A T16C SOT23
Contextual Info: LM71/LM71Q SPI/MICROWIRE 13-Bit Plus Sign Temperature Sensor General Description The LM71 is a low-power, high-resolution digital temperature sensor with an SPI and MICROWIRE compatible interface, available in the 5-pin SOT23 or the 6-pin LLP no pull back

AD5327

Abstract: AD7849 AD5372 ad5627 AD5628 ad7112 AD7808 DAC8413 AD5390 AD7248
Contextual Info: 型号 AD5379 AD5371 新 AD569 位数 输出 接口 14 40 SPI, parallel 108 引脚 CSP_BGA SPI, LVDS 80 引脚 LQFP, 100 引脚 CSP_BGA 14 16 AD669 16 40 1 Parallel 1 Parallel 封装 描述 型号 denseDAC; 用户可编程增益与失调；17.5 V输出范围

Contextual Info: LogiCORE IP SPI-4.2 v13.0 DS823 March 20, 2013 Product Specification Introduction LogiCORE IP Facts Core Specifics Device Family 1 Kintex-7, Virtex-7 Supported User Interface AXI4-Lite and AXI4-Stream Resources Used (2) Alignment Type FPGAs The Xilinx SPI-4.2 (PL4) core implements and is

AD5327

Abstract: AD5805 AD5065 AD7801 AD5300 AD5301 AD5302 AD5330 AD5337 AD557
Contextual Info: Precision DACs Part Number Bits Outputs Interface Package Price @ 1k $U.S. Description Low Voltage, Single Supply (Unipolar Voltage Output with Operation at 5 V and Below) AD5300 8 1 SPI 6-lead SOT-23 1.12 140 A typ at 5 V AD5601 8 1 SPI 6-lead SC70 0.89

AD5327

Abstract: AD5676R
Contextual Info: Precision DACs Part Number Resolution Bits Outputs Interface Package Comments Single-Supply, Low Voltage Output (≤5 V) 140 A typ at 5 V AD5300 8 1 SPI 6-lead SOT-23 AD5601 8 1 SPI 6-lead SC70, 6-lead LFCSP AD5301 8 1 I2C 6-lead SOT-23 AD5602 8 1 6-lead SC70, 6-lead LFCSP

sdc 606

Abstract: EP4GX230KF40C2 EP3SL150F1152C2 hsmc connector altera SOP top marking Stratix II GX FPGA Development Board Reference Manual
Contextual Info: AN 606: POS-PHY Level 4 SPI-4.2 Loopback Reference Design AN-606-1.0 May 2010 The packet over SONET/SDH physical layer (POS-PHY) Level 4—Phase 2 (SPI-4.2) loopback reference design shows how you can transmit and receive data using the Altera POS-PHY Level 4 MegaCore® function and the Stratix® IV and Stratix III

AD5327

Abstract: AD5808 AD7804
Contextual Info: 精密DAC 产品型号 位 输出 接口 封装 报价 千片订量， 美元/片 描述 低压单电源(单极性电压输出，工作电压等于或小于5 V) AD5300 8 1 SPI 6引脚 SOT-23 1.12 140 A (典型值，5 V) AD5601 8 1 SPI 6引脚 SC70 0.89

DIODE SMD c336

Abstract: xcf025 xcf02sv020 b30 c300 DIODE cd c326 MOLEX 87832-1420 SMD fuse P200 xcf02sv020c smdc110f XCF025V
Contextual Info: High Speed Deserialization Board HSDB HSC-ADC-FPGA FUNCTIONAL BLOCK DIAGRAM MULTI-CHANNEL ADC EVALUATION BOARD POWER SUPPLY SERIAL LVDS PER ADC FILTERED ANALOG INPUT CLOCK CIRCUIT HSC-ADC-FPGA HSC-ADC-EVALA/B-DC +3V XILINX FPGA XC2V250 FIFO1 32k SPI CLOCK INPUT

Contextual Info: FemtoClock Crystal-to-LVDS Frequency Synthesizer ICS844256-24 PRELIMINARY DATA SHEET General Description Features The ICS844256-24 is a 6 differential output LVDS Synthesizer designed to generate reference clocks for SPI-4.2 and XAUI/XGMII 10Gb Ethernet interfaces. Using a 31.25MHz, 18pF parallel resonant

d 9329

Abstract: ic 9399 g
Contextual Info: 14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter AD9739A FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF DCO DATA LATCH LVDS DDR RECEIVER CLK DISTRIBUTION DIV-BY-4 IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK

Contextual Info: CDCUN1208LP www.ti.com SCAS928 – MAY 2012 400 MHz Low Power 2:8 Fan-Out Buffer with Universal Inputs and Outputs Check for Samples: CDCUN1208LP FEATURES • 1 • • • • 2 Configuration Options via pins or SPI/I C : – Input Type (HCSL, LVDS, LVCMOS)

spartan3 fpga development boards

Abstract: M25PXX XCF08S ddr spi flash XCF16S PLCC-48 footprint spi flash m25pxx W25PXX XC3S1000 XC3S1500
Contextual Info: LOW-COST FPGA CONFIGURATION VIA INDUSTRY-STANDARD SPI SERIAL FLASH & LatticeECP/EC FPGAs A Lattice Semiconductor White Paper June 2004 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: 503 268-8000 www.latticesemi.com

PS306

Contextual Info: Multiservice Clock Generator AD9551 Preliminary Technical Data FEATURES OVERVIEW Translation between any two standard network rates Dual reference inputs and dual clock outputs Pin programmable for standard network rate translation SPI programmable for arbitrary rational rate translation

Contextual Info: Multiservice Clock Generator AD9551 Preliminary Technical Data FEATURES OVERVIEW Translation between any two standard network rates Dual reference inputs and dual clock outputs Pin programmable for standard network rate translation SPI programmable for arbitrary rational rate translation